WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 55

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Programmer’s Visible State—82577 GbE PHY
8.2
8.3
Register bits are designated by a dot followed by a number after the register address.
Thus, bit 4.16.2 is page 4, register 16 and bit 2. Multi-bit fields follow the MSB, colon,
LSB convention and so bits 4.16.5:4 is page 4, register 16, bits 5:4. All fields in a
register have a name.
Register bits with default values marked with an asterisk * are loaded by the MAC
during the 82577 power up and following reset. Other fields in the same 16-bit register
must be loaded with their default values.
MDIO Access
After PHY reset, a delay of 10 ms is required before any register access using MDIO.
Access using MDIO should be done only when bit 10 in page 769 register 16 is set.
Addressing
Addressing is based on the IEEE 802.3 MII Management Interface specification defined
in clause 22 of 802.3, particularly section 22.2.4.
The 82577 registers are spread over two PHY addresses 01, 02, where general
registers are located under PHY address 01 and the PHY specific registers are at PHY
address 02. The IEEE specification allows five bits for the register access. Registers 0 to
15 are defined by the specification, while registers 16 to 31 are left available to the
vendor. The PHY implements many registers for diagnostic purposes. In addition, the
82577 contains registers controlling the custom interface as well as other the 82577
functions. The total number of registers implemented far exceeds the 16 registers
available to the vendor. When this occurs, a common technique is to use paging. The
82577 registers in PHY address 01, are divided into pages. Each page has 32 registers.
Registers 0-15 are identical in all the pages and are the IEEE defined registers. Register
31 is the page register in all pages of PHY address 01. All other registers are page
specific.
In order to read or write a register, software should define the appropriate PHY
address. For PHY address 01, in order to access registers other than 0-15, software
should first set the page register to map to the appropriate page. Software can then
read or write any register in that page. Setting the page is done by writing page_num x
32 to Register 31. This is because only the 11 MSB’s of register 31 are used for defining
the page. During write to the page register, the five LSB’s are ignored.
In pages 800 and 801, the register address space is more than 32. See
a description of registers addressing in these pages.
Accessing more than 32 registers in PHY address 02, is done without using pages.
Instead, two registers from register address 16 to 31 are used as Address Offset port
and Data port for extended set of registers. See
registers.
section 8.5
for details about these
section 8.9
for
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