WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 132

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Note:
Note:
Note:
125
This register provides extended control of device functionality beyond that provided by
the Device Control (CTRL) register.
If software uses the EE_RST function and needs to retain current configuration
information, the contents of the control registers should be read and stored by
software. Control register values are changed by a read of the NVM, which occurs after
asserting the EE_RST bit.
The EEPROM reset function might read configuration information out of the NVM, which
affects the configuration of PCI configuration space BAR settings. The changes to the
BAR's are not visible unless the system is rebooted and the BIOS is allowed to re-map
them.
The SPD_BYPS bit performs a similar function as the CTRL.FRCSPD bit in that the
device's speed settings are determined by the value software writes to the CRTL.SPEED
bits. However, with the SPD_BYPS bit asserted, the settings in CTRL.SPEED take effect
immediately rather than waiting until after the device's clock switching circuitry
performs the change.
28
29
30
31
Bits
RW
RW
RO
Type
82577 GbE PHY—Intel
0b
0b
0b
0b
Reset
Driver loaded (DRV_LOAD). This bit should be set by the driver after it was
loaded and cleared when the driver unloads or after a soft reset. The
Manageability Controller (MC) loads this bit to indicate that the driver has
loaded.
INT_TIMERS_CLEAR_ENA. When set, this bit enables the clear of the
interrupt timers following an IMS clear. In this state, successive interrupts
occur only after the timers expire again. When cleared, successive
interrupts following IMS clear might happen immediately.
Reserved.
Reserved. Reads as 0.
®
5 Series Express Chipset MAC Programming Interface
Description