WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 172

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

10.2.1.5.4
10.2.1.5.5
10.2.1.5.6
165
This register is used to record statistics about all wake-up packets received. A packet
that matches multiple criteria might set multiple bits. Writing a 1b to any bit clears that
bit.
This register is not cleared when PCI_RST_N is asserted. It is only cleared when
LAN_RST# is de-asserted or when cleared by the driver.
IP Address Valid - IPAV (0x5838; RW)
The IP address valid indicates whether the IP addresses in the IP address table are
valid:
IPv4 Address Table - IP4AT (0x05840 + 8*n (n=1…3); RW)
The IPv4 address table is used to store the three IPv4 addresses for IPv4 request
packet and directed IPv4 packet wake up. It is a 4-entry table with the following
format:
The register at address 0x5840 (n=0) was used in predecessors and reserved in the
Intel
IPv6 Address Table - IP6AT (0x05880 + 4*n (n=0…3); RW)
The IPv6 address table is used to store the IPv6 address for directed IPv6 packet wake
up and manageability traffic filtering. The IP6AT has the following format:
20
21
31:2
0
1
2
3
15:4
16
31:17
31:0
31:0
Bits
Bits
Bits
Bits
®
5 Series Express Chipset.
RW
RW
RO
RO
RW
RW
RW
RO
RW
RO
RW
RW
Type
Type
Type
Type
0b
0b
0x0
0b
0b
0b
0b
0x00
0b
0x00
X
X
Reset
Reset
Reset
Reset
82577 GbE PHY—Intel
FLX4. Flexible Filter 4 Match.
FLX5. Flexible Filter 5 Match.
Reserved.
Reserved.
V41. IPv4 Address 1 Valid.
V42. IPv4 Address 2 Valid.
V43. IPv4 Address 3 Valid.
Reserved.
V60. IPv6 Address Valid.
Reserved.
IPADD. IP Address n (n=1, 2, 3).
IPV6 Address. IPv6 Address bytes n*4…n*4+3 (n=0, 1, 2, 3) while byte 0 is first
on the wire and byte 15 is last.
®
5 Series Express Chipset MAC Programming Interface
Description
Description
Description
Description