WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 154

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Note:
10.2.1.3.13 Receive Descriptor Control - RXDCTL (0x02828; RW)
Note:
Note:
147
This feature operates by initiating a countdown timer upon successfully receiving each
packet to system memory. If a subsequent packet is received BEFORE the timer
expires, the timer is re-initialized to the programmed value and re-starts its
countdown. If the timer expires due to NOT having received a subsequent packet within
the programmed interval, pending receive descriptor write backs are flushed and a
receive timer interrupt is generated.
Setting the value to 0b represents no delay from a receive packet to the interrupt
notification, and results in immediate interrupt notification for each received packet.
Writing this register with FPD set initiates an immediate expiration of the timer, causing
a write back of any consumed receive descriptors pending write back, and results in a
receive timer interrupt in the ICR.
Receive interrupts due to a Receive Absolute Timer (RADV) expiration cancels a
pending RDTR interrupt. The RDTR countdown timer is reloaded but stopped, so as to
avoid generation of a spurious second interrupt after the RADV has been noted, but
might be restarted by a subsequent received packet.
FPD is self-clearing.
This register was not fully validated. Software should set it to 0x0000 during normal
operation.
This register controls the fetching and write back of receive descriptors. The three
threshold values are used to determine when descriptors is read from and written to
host memory. The values might be in units of cache lines or descriptors (each
descriptor is 16 bytes) based on the GRAN flag. If GRAN=zero (specifications are in
cache-line granularity), the thresholds specified (based on the cache line size specified
in the PCI configuration space CLS field) must not represent greater than 31
descriptors.
When (WTHRESH = 0b) or (WTHRESH = 1b and GRAN = 1b) only descriptors with the
RS bit set is written back.
5:0
7:6
13:8
14
15
21:16
23:22
24
31:25
Bits
RW
RO
RW
RW
RW
RW
RO
RW
RO
Type
0x00
0x00
0x00
0b
0b
0x01
0x00
0b
0x00
Reset
82577 GbE PHY—Intel
Prefetch Threshold (PTHRESH).
Reserved.
Host Threshold (HTHRESH).
Reserved.
Reserved.
Write-Back Threshold (WTHRESH).
Reserved.
Granularity (GRAN). Units for the thresholds in this register.
0b = Cache lines.
1b = Descriptors.
Reserved.
®
5 Series Express Chipset MAC Programming Interface
Description