WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 12

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.0
2.1
.
Table 2.
2.2
Note:
2.2.1
5
Interconnects
Introduction
The 82577 implements two interconnects to the MAC:
82577 Interconnect Modes
The 82577 automatically switches the in-band traffic between PCIe and SMBus based
on the system power state.
PCIe-Based
The 82577 PCIe interface is not PCIe compliant. It operates at half of the PCI Express*
(PCIe*) Specification v1.1 (2.5 GT/s) speed. In this datasheet the term PCIe-based is
interchangeable with PCIe. There is no design layout differences between normal PCIe
and the 82577’s PCIe-based interface. Standard PCIe validation tools cannot be used to
validate this interface.
PCIe Interface Signals
The signals used to connect between the MAC and the PHY in this mode are:
S0 and PHY Power Down
S0 and Idle or Link Disc
S0 and active
Sx
Sx and DMoff
• PCIe - A high-speed SerDes interface using PCIe electrical signaling at half speed
• System Management Bus (SMBus) – A very low speed connection for low power
• Serial differential pair running at 1.25 Gb/s for Rx
• Serial differential pair running at 1.25 Gb/s for Tx
• 100 MHz differential clock input to the PHY running at 100 MHz
• Power and clock good indication to the PHY PE_RST_N pin
• Clock control through CLK_REQ_N pin
while keeping the custom logical protocol for active state operation mode.
state mode for manageability communication only. At this low power state mode
the Ethernet link speed is reduced to 10 Mb/s.
System
Not used
Not used
Not used
SMBus
Active
Active
PHY
Power down
Power down
Active
PCIe
Idle
Idle
82577 GbE PHY—Interconnects