WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 144

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

10.2.1.2.4
Note:
137
Interrupt Mask Set/Read Register - IMS (0x000D0; RW)
Reading this register returns which bits have an interrupt mask set. An interrupt is
enabled if its corresponding mask bit is set to 1b, and disabled if its corresponding
mask bit is set to 0b. An interrupt is generated each time one of the bits in this register
is set, and the corresponding interrupt condition occurs. The occurrence of an interrupt
condition is reflected by having a bit set in the Interrupt Cause Read register (see
Section
A particular interrupt might be enabled by writing a 1b to the corresponding mask bit in
this register. Any bits written with a 0b are unchanged.
If software desires to disable a particular interrupt condition that had been previously
enabled, it must write to the Interrupt Mask Clear register (see
rather than writing a 0b to a bit in this register.
When the CTRL_EXT.INT_TIMERS_CLEAR_ENA bit is set, then following writing all 1b's
to the IMS register (enable all interrupts) all interrupt timers are cleared to their initial
value. This auto clear provides the required latency before the next INT event.
0
1
2
3
4
5
6
7
8
9
11:10
12
13
14
15
16
17
18
19
20
21
22
31:23
Bit
10.2.1.3).
RWS
RWS
RWS
RO
RWS
RWS
RWS
RWS
RWS
RWS
RO
RWS
RO
RWS
RWS
RWS
RWS
RWS
RWS
RWS
RO
RWS
RO
Type
82577 GbE PHY—Intel
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
00b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0x0
Reset
TXDW. Sets transmit descriptor written back.
TXQE. Sets transmit queue empty.
LSC. Sets link status change.
Reserved.
RXDMT0. Sets mask for receive descriptor minimum threshold hit.
DSW. Sets mask for block software write accesses.
RXO. Sets mask for receiver overrun. Set on receive data FIFO overrun.
RXT0. Sets mask for receiver timer interrupt.
LCAPD. Sets mask for LCAPD interrupt. LCAPD mask is set after reset to
enable LCAPD interrupt (driven by Intel
MDAC. Sets mask for MDIO access complete interrupt.
Reserved.
PHYINT. Sets mask for PHY interrupt.
Reserved.
Reserved.
TXD_LOW. Sets the mask for transmit descriptor low threshold hit.
SRPD. Sets mask for small receive packet detection.
ACK. Sets the mask for receive ACK frame detection.
MNG. Sets mask for manageability event interrupt.
Reserved.
Reserved.
Reserved.
ECCER Sets mask for uncorrectable EEC error
Reserved. Should be written with 0b to ensure future compatibility.
®
5 Series Express Chipset MAC Programming Interface
Description
®
5 Series Express Chipset).
Section
10.2.1.3.6),