WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 97

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Programmer’s Visible State—82577 GbE PHY
Figure 9.
Table 79.
Figure 9
represents the internally stored ordering of the received destination address. Note that
Byte 1 bit 0 shown in
multicast table array in this diagram match a multicast offset in the CTRL register
equals 00b. The complete multicast offset options are:
Multicast Table Array Algorithm
Flexible Filter Value Table LSB– FFVT_01 PHY Address 01, Page 800, Registers
256 + 2*n (n=0…127)
There are 128 filter values. The flexible filter value is used to store the one value for
each byte location in a packet for each flexible filter. If the corresponding mask bit is
one, then the flexible filter compares the incoming data byte to the values stored in this
table.
RW
RW
Attribute
shows the multicast lookup algorithm. The destination address shown
7:0
15:8
Bit(s)
00b
01b
10b
11b
Multicast
Offset
Figure 9
X
X
Initial Value
DA[47:38] = Byte 6 bits 7:0, Byte 5 bits 1:0
DA[46:37] = Byte 6 bits 6:0, Byte 5 bits 2:0
DA[45:36] = Byte 6 bits 5:0, Byte 5 bits 3:0
DA[43:34] = Byte 6 bits 3:0, Byte 5 bits 5:0
is the first on the wire. The bits that are directed to the
Bits Directed to the Multicast Table Array
Value 0
Value of filter 0 byte n (n=0, 1… 127).
Value 1
Value of filter 1 byte n (n=0, 1… 127).
Description
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