WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 106

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

99
7:6
5
4
3
2
1
0
Bits
PHYT
Reserved
FRCSPD
FD
Reserved
CLK_CNT_1_4
Dynamic Clock
gating
Name
00b
01
0b
0b
1b
0b
1b
Default
PHY Device Type
Indicates that the PHY is connected to the MAC and resulted mode
of operation of the MAC/PHY link buses.
00b = 82577.
01b = Reserved.
10b = Reserved.
11b = Reserved.
Reserved, should be set to 1b.
Default setting for the Force Speed bit in the Device Control
register (CTRL[11]).
Default setting for the Full Duplex bit in the Device Control register
(CTRL[0]). The hardware default value is 1b.
Reserved, set to 0b.
When set, automatically reduces DMA frequency. Mapped to the
Device Status register (STATUS[31]).
When set, enables dynamic clock gating of the DMA and MAC
units. This bit is loaded to the DynCK bit in the CTRL_EXT register.
82577 GbE PHY—Non-Volatile Memory (NVM)
Description