WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 135

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Intel
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
9:7
10
11
12
13
14
15
19:16
20
26:21
27
31:28
Bits
RW/SN
RW/SN
RW/SN
RW/SN
RW/SN
RW/SN
RW/SN
RW/SN
RW/SN
RW/SN
RW/SN
RW/SN
Type
0x0
0b
0b
0b
0b
0b
0b
0b
0b
00b
0x0
0x0
Reset
Reserved.
Enable MDIO Watchdog Timer (MDIOWatchEna). When set to 0b, the
100 ms MDIO watchdog timer is enabled.
Default NVM setting = 1b.
Update DMA PTR.
0b = The pointer to the packet header is updated at the start of the
packet.
1b = The pointer to the packet header is updated at the end of the
previous packet (legacy behavior).
Default NVM setting = 0b.
MAC Synchronization.
1b = In GbE mode, the MAC does not need to wait for synchronization
between clock domains (the clock domains are the same) and the
synchronization stage is skipped.
0b = The synchronization stage is not skipped.
When operating in 10/100 Mb/s, the synchronization is still needed,
therefore it is never skipped.
Default NVM setting = 0b.
Reserved.
Auto PHYINT Clear.
0b = Clears the interrupt indication from the 82577 immediately after the
ICR is read.
Default NVM setting = 0b.
Drop Rx Packet.
0b = Causes packet dropping when it comes, if no descriptors while early
receive is enabled.
Default NVM setting = 0b.
Reserved.
Disable CLK gate Enable Due to D3hot. When set, disables assertion of
bb_clkgaten due to D3hot.
Default NVM setting = 0b.
Reserved.
Software LCD Config Enable. This bit has no impact on hardware but
rather influences the software flow. The software should initialize the
82577 using the extended configuration image in the NVM only when both
the Software LCD Config Enable bit is set and the LCD Write Enable bit in
the EXTCNF_CTRL register is cleared.
Reserved.
Description
128