WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 58

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

8.5
Table 10.
51
PHY Registers (Page 0)
Control Register - Address 0
15
14
13
12
11
10
9
8
7
6
5:0
Bits
Reset
Loopback
Speed Select
(LSB)
Auto-
Negotiation
Enable
Power Down
Isolate
Restart Auto-
Negotiation
Duplex Mode
Collision Test
Speed
Selection
(MSB)
Reserved
Field
R/W, SC
R/W
R/W
R/W
R/W
R/W
R/W,SC
R/W
R/W
RO
R/W
Type
0b
0b
X
0b
0b
0b
X
0b
X
Always 0x0
1b
Default
Writing a 1b to this bit causes immediate PHY reset. Once
the operation completes, this bit clears to 0b automatically
1b = PHY reset.
0b = Normal operation.
This is the master enable for digital and analog loopback as
defined by the IEEE standard. The exact type of loopback is
determined by the Loopback Control register (19). See
section 7.5
1b = Enables loopback.
0b = Disables loopback.
The speed selection address 0 (bits 13 and 6) can be used
to configure the link manually. Setting these bits has no
effect unless address 0 (bit 12) is cleared.
11b = Reserved.
10b = 1000 Mb/s.
01b = 100 Mb/s.
00b = 10 Mb/s.
When this bit is cleared, the link configuration is
determined manually.
1b = Enables auto-negotiation process.
0b = Disables auto-negotiation process.
1b = Power down.
0b = Normal operation.
Setting this bit isolates the PHY from the MII or GMII
interfaces.
1b = Isolates the PHY from MII.
0b = Normal operation.
1b = Restarts auto-negotiation process.
0b = Normal operation.
This bit might be used to configure the link manually.
Setting this bit has no effect unless address 0 (bit 12) is
cleared.
1b = Full-duplex.
0b = Half-duplex.
Enables IEEE 22.2.4.1.9 collision test.
1b = Enable collision test.
0b = Disable collision test.
See description in bit 13.
Reserved, always set to 0x0.
82577 GbE PHY—Programmer’s Visible State
for more details).
Description