WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 169

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Intel
Note:
Note:
10.2.1.4.11 Transmit Absolute Interrupt Delay Value-TADV (0x0382C; RW)
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
WTHRESH = 0..3
HTHRESH = 0..4
For any WTHRESH value other than zero - The packet and absolute timers must get a
non zero value for the WTHRESH feature to take affect.
Since the default value for write-back threshold is zero, descriptors are normally
written back as soon as they are processed. WTHRESH must be written to a non-zero
value to take advantage of the write-back bursting capabilities of the MAC. If the
WTHRESH is written to a non-zero value then all of the descriptors are written back
consecutively no matter the setting of the RS bit.
Since write back of transmit descriptors is optional (under the control of RS bit in the
descriptor), not all processed descriptors are counted with respect to WTHRESH.
Descriptors start accumulating after a descriptor with RS is set. Furthermore, with
transmit descriptor bursting enabled, all of the descriptors are written back
consecutively no matter the setting of the RS bit.
LWTHRESH controls the number of pre-fetched transmit descriptors at which a transmit
descriptor-low interrupt (ICR.TXD_LOW) is reported. This might enable software to
operate more efficiently by maintaining a continuous addition of transmit work,
interrupting only when hardware nears completion of all submitted work. LWTHRESH
specifies a multiple of eight descriptors. An interrupt is asserted when the number of
descriptors available transitions from (threshold level=8*LWTHRESH)+1  (threshold
level=8*LWTHRESH). Setting this value to zero disables this feature.
The transmit interrupt delay timer (TIDV) might be used to coalesce transmit
interrupts. However, it might be necessary to ensure that no completed transmit
remains unnoticed for too long an interval in order ensure timely release of transmit
buffers. This register might be used to ENSURE that a transmit interrupt occurs at
some predefined interval after a transmit is completed. Like the delayed-transmit timer,
the absolute transmit timer ONLY applies to transmit descriptor operations where (a)
interrupt-based reporting is requested (RS set) and (b) the use of the timer function is
requested (IDE is set).
This feature operates by initiating a countdown timer upon successfully transmitting
the buffer. When the timer expires, a transmit-complete interrupt (ICR.TXDW) is
generated. The occurrence of either an immediate (non-scheduled) or delayed transmit
timer (TIDV) expiration interrupt halts the TADV timer and eliminate any spurious
second interrupts.
Setting the value to zero disables the transmit absolute delay function. If an immediate
(non-scheduled) interrupt is desired for any transmit descriptor, the descriptor IDE
should be set to zero.
15:0
31:16
Bits
RW
RO
Type
0x0
0x0
Reset
Interrupt Delay Value (IDV). Counts in units of 1.024 ms. (0b = disabled)
Reserved. Reads as 0b. Should be written to 0b for future compatibility.
Description
162