WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 124

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

10.2.1
Table 18.
117
PCI Configuration and Status Registers - CSR Space
All configuration registers are listed in
grouping and are not necessarily listed in order that they appear in the address space.
Register based legend:
Register Summary
0x00000
0x00008
0x0000C
0x00018
0x00020
0x00028
0x0002C
0x00038
0x00170
0x05F40
0x00F00
0x00F08
0x00F10
0x00F18
0x01000
0x01008
0x0100C
0x01004
• RW - Read write register.
• RO - Read only register.
• RO/CR - Read only register, clear on read.
• RO/V - Read only register, read status is not constant
• RW/RO - Read write by firmware; read only by software.
• RWC - Read write clear registers. Writing 0b has no affect. Writing 1b clears the
• RW/V – Read write register. This bit self-clears immediately.
• RW/SN – Read write register initial value loaded from NVM.
• RC/WC - Read write clear registers. Writing 0b has no affect. Writing 1b clears the
• RWC/CR/V – Read write register clear on read, clear on write.
• WO - Write only registers. Reading from these registers does not reflect any
appropriate fields (see detailed description of the specific registers).
appropriate fields. Note that a read might also clear the register depending on
enablement (see appropriate registers).
meaningful data. Generally this would be all zero's (see detailed description of
appropriate registers).
Offset
PCIEANACFG
PBECCSTS
PBEEI
CTRL
STATUS
STRAP
CTRL_EXT
MDIC
FEXTNVM
FEXT
BUSNUM
FCTTV
FCRTV
EXTCNF_CTRL
EXTCNF_SIZE
PHY_CTRL
PBA
PBS
82577 GbE PHY—Intel
Abbreviation
General Register Descriptions
Device Control Register
Device Status Register
Strapping Option Register
Extended Device Control Register
MDI Control Register
Future Extended NVM Register
Future Extended Register
Device and Bus Number
Flow Control Transmit Timer Value
Flow Control Refresh Threshold Value
Extended Configuration Control
Extended Configuration Size
PHY Control Register
PCIE Analog Configuration
Packet Buffer Allocation
Packet Buffer Size
Packet Buffer ECC Status
Packet Buffer ECC Error Inject
Table
®
5 Series Express Chipset MAC Programming Interface
18. These registers are ordered by
Name
RW
RW
RW
RW
RO
RO
RW
RW
RW
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
10.2.1.1.1
10.2.1.1.2
10.2.1.1.3
10.2.1.1.4
10.2.1.1.5
10.2.1.1.6
10.2.1.1.7
10.2.1.1.8
10.2.1.1.9
10.2.1.1.10
10.2.1.1.11
10.2.1.1.12
10.2.1.1.13
10.2.1.1.14
10.2.1.1.15
10.2.1.1.16
10.2.1.1.17
10.2.1.1.18
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