WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 133

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Intel
10.2.1.1.5
Note:
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
MDI Control Register - MDIC (0x00020; RW)
This register is used by software to read or write Management Data Interface (MDI)
registers in the 82577.
Internal logic uses MDIC to communicate with the 82577. All fields in these registers
are indicated as "/V" since the internal logic might use them to access the 82577. Since
hardware uses this register, all hardware, software and firmware must use semaphore
logic (the ownership flags) before accessing the MDIC.
For an MDI read cycle the sequence of events is as follows:
where the Z stands for the MAC tri-stating the MDIO signal.
15:0
20:16
25:21
27:26
28
29
30
31
1. The CPU performs a write cycle to the MII register with:
2. The MAC applies the following sequence on the MDIO signal to the 82577:
3. The 82577 returns the following sequence on the MDIO signal:
4. The MAC discards the leading bit and places the following 16 data bits in the MII
5. The MAC asserts an Interrupt indicating MDI done, if the Interrupt Enable bit was
6. The MAC sets the Ready bit in the MII register indicating the read is complete.
Bits
register.
set.
— Ready = 0b
— Interrupt Enable bit set to 1b or 0b
— Op-Code = 10b (read)
— PHYADD = The 82577 address from the MDI register
— REGADD = The register address of the specific register to be accessed (0
— <PREAMBLE><01><10><PHYADD><REGADD><Z>
— <0><DATA><IDLE>
through 31)
RW/V
RW/V
RW/V
RW/V
RW/V
RW/V
RW/V
RO
Type
X
00b
1b
0b
0b
0x0
0x0
0b
Reset
Data (DATA). In a Write command, software places the data bits and the
MAC shifts them out to the 82577. In a Read command, the MAC reads
these bits serially from the 82577 and software can read them from this
location.
PHY Register address (REGADD). For example, register 0, 1, 2, … 31.
PHY Address (PHYADD).
Op-code (OP).
01b = MDI write.
10b = MDI read.
Other values are reserved.
Ready bit (R). Set to 1b by the MAC at the end of the MDI transaction (for
example, indicates a read or write completed). It should be reset to 0b by
software at the same time the command is written.
Interrupt Enable (I). When set to 1b by software, it causes an interrupt to
be asserted to indicate the end of an MDI cycle.
Error (E). This bit set is to 1b by hardware when it fails to complete an
MDI read. Software should make sure this bit is clear (0b) before making
a MDI read or write command.
Reserved. Write as 0b for future compatibility.
Description
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