WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 136

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

10.2.1.1.7
C
10.2.1.1.8
10.2.1.1.9
129
Future Extended Register - FEXT (0x0002C; RW)
This register is initialized to a hardware default only at LAN_RST# reset. Software
should not modify these fields to values other than their recommended values.
Device and Bus Number - BUSNUM (0x00038; RO)
Flow Control Transmit Timer Value - FCTTV (0x00170; RW)
0
1
3:2
7:4
8
9
10
11
12
13
17:14
31:18
7:0
10:8
15:11
23:16
31:24
15:0
31:16
Bits
Bit
Bit
RO
RO/V
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RW
RO
Type
Type
Type
82577 GbE PHY—Intel
0b
0b
00b
0x0
0b
0b
0b
0b
0b
0b
0x0
0x0
0x0
000b
0x19
0x0
0x0
X
0x0
Reset
Reset
Reset
Reserved.
Reserved.
Reserved.
Reserved.
Hardware/Software CRC Mismatch Trigger. When set to 1b the MAC
generates a trigger signal each time there is a mismatch between the
software calculated CRC and hardware calculated CRC.
This feature is ignored when CRC calculation is off-loaded to hardware.
Write Disable Ghost and DMA RAMs on CRC Mismatch. When set to 1b,
disables any writes to the following RAMs in the event of CRC mismatch
until reset:
When set to 1b, enables the data visibility of the ghost read PCI descriptor
and PCI data RAMs to the NOA.
Visibility in/out read data select. 1b = in.
Bit 10 of the FEXT register must be set to 1b.
Visibility data/desc read Ram select. 1b = data.
Bit 10 of the FEXT register must be set to 1b.
When set to 1b, the ghost read RAMs are readable by the slave bus.
Must be set to 0x0.
Future Extended. Reserved for future setting.
Reserved.
Function Number. The MAC is a single PCI function being function 0.
Device Number. During normal operation, the MAC has a pre-defined
device number equal to 25 (0x19).
Bus Number. The MAC captures its bus number during host configuration
write cycles type 0 aimed at the device. This field is initialized by
LAN_RST# reset, PCI reset, and D3 to D0 transition.
Reserved.
Transmit Timer Value (TTV).
Included in XOFF frame.
Reserved. Read as 0b. Should be written to 0b for future compatibility.
• Ghost read PCI descriptor
• Ghost read PCI data
• The four RAMs in the descriptor engine
• The packet buffer
®
5 Series Express Chipset MAC Programming Interface
Description
Description
Description