WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 188

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 22.
Note:
Figure 23.
Note:
181
XTAL Timing Diagram
Figure 23
XTAL_IN because the rail-to-rail source is +3.3V. In this case the oscillator must meet
the requirements listed in
a conditioning circuit must be provided to enable the amplifier bias operating point to
be achieved. If required, contact your Intel representative for information about
implementing the conditioning circuit. For placement and layout guidelines, refer to the
Intel® 5 Series Family Platform Design Guide (PDG).
Peak-to-peak voltage presented at the XTAL1 input cannot exceed 3.6 Vdc. Also, the
XTAL_OUT pin is a No Connect for the oscillator.
Clock Oscillator Schematic
This is an example only. Refer to the appropriate reference schematic for detailed
connections.
shows a direct connection between CLK Oscillator Out and the 82577
Note: The 33 ohm resistor is not required if total routing
3.3 V dc
C1
length is less than 2000 mils (50.8 mm).
VDD3p3
Oscillator
Table
CLK
88. If the oscillator source is not rail-to-rail +3.3V, then
Out
33 ohm
82577 GbE PHY—Electrical and Timing Specifications
XTAL_IN
PHY