WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 71

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Programmer’s Visible State—82577 GbE PHY
Table 33.
Interrupt Status Register - Address 25
15:11
10
9
8
7
6
5
4
3
2
1
0
Bits
Reserved
TDR/IP Phone
MDIO Sync Lost
Auto-Negotiation
Status Change
CRC Errors
Next Page Received
Error Count Full
FIFO Overflow/
Underflow
Receive Status Change
Link Status Change
Automatic Speed
Downshift
MII Interrupt Pending
Field
RO, LH
RO, LH
RO, LH
RO, LH
RO, LH
RO, LH
RO, LH
RO, LH
RO, LH
RO, LH
RO, LH
Type
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Default
Reserved.
1b = Event completed.
0b = Event has not completed.
If the management frame preamble is
suppressed (MF preamble suppression,
Register 0, bit 6), it is possible for the PHY to
lose synchronization if there is a glitch at the
interface. The PHY can recover if a single
frame with a preamble is sent to the PHY. The
MDIO sync lost interrupt can be used to
detect loss of synchronization and, thus,
enable recovery.
1b = Event has occurred.
0b = Event has not occurred.
1b = Event has occurred.
0b = Event has not occurred.
1b = Event has occurred.
0b = Event has not occurred.
1b = Event has occurred.
0b = Event has not occurred.
1b = Event has occurred.
0b = Event has not occurred.
1b = Event has occurred.
0b = Event has not occurred.
1b = Event has occurred.
0b = Event has not occurred.
1b = Event has occurred.
0b = Event has not occurred.
1b = Event has occurred.
0b = Event has not occurred.
An event has occurred and the corresponding
interrupt mask bit is enabled (set to 1b).
1b = Interrupt pending.
0b = No interrupt pending.
Description
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