WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 34

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.2
6.2.1
6.3
6.3.1
6.3.1.1
27
The following sections describe requirements in specific power states.
Power Delivery
The 82577 operates from a 3.3 Vdc external power rail (see
1.0 Vdc Supply
The 1.0 Vdc rail can be supplied in one of two ways (see
Power Management
Global Power States
The 82577 transitions between power states based on a status packet received over
the interconnect and based on the Ethernet link state. The following power states are
defined:
Power Up
Defined as the period from the time power is applied to the 82577 and until the 82577
powers up its PHY. the 82577 should consume less than ~40 mA during this period.
Following the 82577 PHY entering reset, the power-up sequence is considered done
and the requirement is removed.
• An external power supply not dependent on support from the 82577. For example,
• A discrete LVR solution, where the base current of PNP power transistor is driven by
• Power Up – Defined as the period from the time power is applied to the 82577 and
• Active 10/100/1000 Mb/s – Ethernet link is established with a link partner at
• Idle 10/100/1000 Mb/s - Ethernet link is established with a link partner at any
• Cable Disconnect – The PHY identified that a cable is not connected. The 82577
• Power Down (LAN Disable) – Entry into power down is initiated by the MAC by
•
the Intel
supply.
the 82577, while the power transistor is placed externally.
until the 82577 powers up its PHY. The 82577 needs to consume less than 40 mA
during this period.
any of 10/100/1000 Mb/s speed. The 82577 is either transmitting/receiving data or
is capable of doing so without delay (for example, no clock gating that requires
lengthy wake).
of 10/100/1000 Mb/s speed. The 82577 is not actively transmitting or receiving
data and might enter a lower power state (for example, the custom interface can
be in electrical idle).
signals the MAC that the link is down. The PHY might enter energy detect mode or
the MAC might initiate a move into active power down mode (sD3).
setting the LAN_DISABLE_N pin to zero. The 82577 loses all functionality in this
mode other than the ability to power up again.
®
5 Series Express Chipset 1.05 Vdc SVR can be tied to the 1.0 Vdc PHY
82577 GbE PHY—Power Management and Delivery
Figure
Figure
4):
7).