WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 143

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Intel
Note:
10.2.1.2.3
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
Inversely, inter-interrupt interval value can be calculated as:
inter-interrupt interval = (256 x 10
The optimal performance setting for this register is very system and configuration
specific. An initial suggested range for the interval value is 65--5580 (28B - 15CC).
When working at 10/100 Mb/s and running at ¼ clock the interval time is multiplied by
four.
Interrupt Cause Set Register - ICS (0x000C8; WO)
Software uses this register to set an interrupt condition. Any bit written with a 1b sets
the corresponding interrupt. This results in the corresponding bit being set in the
Interrupt Cause Read register (see
one of the bits in this register is set, and the corresponding interrupt is enabled via the
Interrupt Mask Set/Read register (see
Bits written with 0b are unchanged.
0
1
2
3
4
5
6
7
8
9
11:10
12
13
14
15
16
17
18
19
20
21
22
31:23
Bit
WO
WO
WO
RO
WO
WO
WO
WO
WO
WO
RO
WO
RO
WO
WO
WO
WO
WO
WO
WO
RO
WO
RO
Type
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Reset
TXDW. Sets transmit descriptor written back.
TXQE. Sets transmit queue empty.
LSC. Sets link status change.
Reserved.
RXDMT. Sets receive descriptor minimum threshold hit.
DSW. Sets block software write accesses.
RXO. Sets receiver overrun. Set on receive data FIFO overrun.
RXT. Sets receiver timer interrupt.
LCAPD. Sets LCAPD interrupt.
MDAC. Sets MDIO access complete interrupt.
Reserved.
PHYINT. Sets PHY interrupt.
Reserved.
Reserved.
TXD_LOW. Transmit descriptor low threshold hit.
Small Receive Packet Detected (SRPD) and transferred.
ACK. Set receive ACK frame detected.
MNG. Set the manageability event interrupt.
Reserved.
Reserved.
Reserved.
ECCER Set uncorrectable EEC error.
Reserved. Should be written with 0b to ensure future compatibility.
-9
Section
sec x interrupts/sec)
Section
10.2.1.3), and an interrupt is generated if
10.2.1.3.5).
Description
-1
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