WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 148

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 85.
141
LPE controls whether long packet reception is permitted. Hardware discards long
packets if LPE is 0b. A long packet is one longer than 1522 bytes. If LPE is 1b, the
maximum packet size that the device can receive is bytes.
RDMTS{1,0} determines the threshold value for free receive descriptors according to
the following table:
RDMTS Values
BSIZE controls the size of the receive buffers and permits software to trade-off
descriptor performance versus required storage space. Buffers that are 2048 bytes
require only one descriptor per receive packet maximizing descriptor efficiency. Buffers
that are 256 bytes maximize memory efficiency at a cost of multiple descriptors for
packets longer than 256 bytes.
PMCF controls the DMA function of the MAC control frames (other than flow control). A
MAC control frame in this context must be addressed to either the MAC control frame
multicast address or the station address, match the type field and NOT match the
PAUSE opcode of 0x0001. If PMCF = 1b then frames meeting this criteria is DMA'd to
host memory.
The SECRC bit controls whether hardware strips the Ethernet CRC from the received
packet. This stripping occurs prior to any checksum calculations. The stripped CRC is
not DMA'd to host memory and is not included in the length reported in the descriptor.
00b
01b
10b
11b
RDMTS
82577 GbE PHY—Intel
1/2
1/4
1/8
Reserved
Free Buffer Threshold
®
5 Series Express Chipset MAC Programming Interface