WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 167

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Intel
Note:
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
This feature operates by initiating a countdown timer upon successfully transmitting
the buffer. If a subsequent transmit delayed-interrupt is scheduled BEFORE the timer
expires, the timer is re-initialized to the programmed value and re-starts its
countdown. When the timer expires, a transmit-complete interrupt (ICR.TXDW) is
generated.
Setting the value to zero is not allowed. If an immediate (non-scheduled) interrupt is
desired for any transmit descriptor, the descriptor IDE should be set to zero.
The occurrence of either an immediate (non-scheduled) or absolute transmit timer
interrupt halts the TIDV timer and eliminate any spurious second interrupts.
Transmit interrupts due to a Transmit Absolute Timer (TADV) expiration or an
immediate interrupt (RS/RSP=1b, IDE=0b) cancels a pending TIDV interrupt. The TIDV
countdown timer is reloaded but halted, though it might be restarted by a processing a
subsequent transmit descriptor.
Writing this register with FPD set initiates an immediate expiration of the timer, causing
a write back of any consumed transmit descriptors pending write back, and results in a
transmit timer interrupt in the ICR.
FPD is self-clearing.
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