NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 100

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 35.
5.2.1.5
Table 36.
5.2.1.6
Intel
DS
100
®
6300ESB I/O Controller Hub
SYNC Bit Definition (Sheet 2 of 2)
SYNC Time-Out
There are several error cases that may occur on the LPC I/F. The following table
indicates the failing case and the Intel
Response to Sync Failures
There may be other peripheral failure conditions, however these are not handled by the
Intel
SYNC Error Indication
The SYNC protocol allows the peripheral to report an error through the LAD[3:0] =
‘1010b’ encoding. The intent of this encoding is to give peripherals a method of
communicating errors to aid higher layers with more robust error recovery.
When the Intel
transferred in the next two nibbles. This data may be invalid, but it must be transferred
by the peripheral. When the Intel
data had already been transferred.
In the case of multiple byte cycles, such as for memory and DMA cycles, an error SYNC
terminates the cycle. Therefore, when the Intel
bytes from a device, and if the device returns the error SYNC in the first byte, the other
three bytes will not be transferred.
NOTE: All other combinations are Reserved.
Intel
device drives a valid SYNC after 4 consecutive clocks. This could
occur when the processor tries to access an I/O location to which no
device is mapped.
Intel
peripheral drives more than 8 consecutive valid SYNC to insert wait-
states using the Short (‘0101b’) encoding for SYNC. This could occur
when the peripheral is not operating properly.
Intel
peripheral drives an invalid SYNC pattern. This could occur when the
peripheral is not operating properly or when there is excessive noise
on the LPC I/F.
Bits[3:0]
0110
1001
1010
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®
6300ESB ICH starts a Memory, I/O, or DMA cycle, but no
6300ESB ICH drives a Memory, I/O, or DMA cycle, and a
6300ESB ICH starts a Memory, I/O, or DMA cycle, and a
6300ESB ICH.
Long Wait: Part indicating wait-states, and many wait-states will be added. This
encoding driven by the Intel
the Short Wait (0101).
Ready More (Used only by peripheral for DMA cycle): SYNC achieved with
no error and more DMA transfers desired to continue after this transfer. This
value is valid only on DMA transfers and is not allowed for any other type of
cycle.
Error: Sync achieved with error. This is generally used to replace the SERR# or
IOCHK# signal on the PCI/ISA bus. It indicates that the data is to be transferred,
but there is a serious error in this transfer. For DMA transfers, this not only
indicates an error, but also indicates DMA request deassertion and no more
transfers desired for that channel.
®
6300ESB ICH is reading data from a peripheral, data will still be
Possible Sync Failure
®
6300ESB ICH is writing data to the peripheral, the
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®
6300ESB ICH response:
6300ESB ICH for bus master cycles, rather than
Indication
®
6300ESB ICH is transferring four
Order Number: 300641-004US
Intel
aborts the cycle after
the fourth clock.
Continues waiting
Intel
aborts the cycle when
the invalid Sync is
recognized.
Intel
Intel
®
®
®
Response
6300ESB ICH
6300ESB ICH
®
6300ESB ICH
6300ESB ICH—5
November 2007