NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 408

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 293. SMI_STS—SMI Status Register (Sheet 1 of 2)
Intel
DS
408
31:2
22:1
Bits
Default Value:
23
18
17
16
15
14
13
12
I/O Address:
4
9
®
6300ESB I/O Controller Hub
Lockable:
Device:
DEVMON_STS: Device
LEGACY_USB2_STS
(SMBUS_SMI_STS)
SMBus SMI Status
SERIRQ_SMI_STS
INTEL_USB2_STS
PERIODIC_STS
WDT_SMI_STS
Monitor Status
Reserved
Reserved
TCO_STS
31
PMBASE + 34h
00000000h
No
Name
Reserved.
0 = SMI# not caused by WDT 1
1 = Indicates the SMI# was caused by the WDT 1
Reserved.
This non-sticky read-only bit is a logical OR of each of the SMI
status bits in the Intel-Specific USB EHCI SMI Status Register
ANDed with the corresponding enable bits. This bit will not be
active when the enable bits are not set. Writes to this bit will
have no effect.
This non-sticky read-only bit is a logical OR of each of the SMI
status bits in the USB EHCI Legacy Support Register ANDed
with the corresponding enable bits. This bit will not be active
when the enable bits are not set. Writes to this bit will have
no effect.
0 = This bit is cleared by writing a 1 to its bit position. This bit
1 = Indicates that the SMI# was caused by:
0 = SMI# was not caused by SERIRQ decoder. This is not a
1 = Indicates that the SMI# was caused by the SERIRQ
0 = This bit is cleared by writing a 1 to its bit position.
1 = This bit will be set at the rate determined by the
0 = SMI# not caused by TCO logic.
1 = Indicates the SMI# was caused by the TCO logic. Note
0 = SMI# not caused by Device Monitor.
1 = Set under any of the following conditions:
is set from the 64 KHz clock domain used by the SMBus.
Software must wait at least 15.63 us after the initial
assertion of this bit before clearing it.
1. The SMBus Slave receiving a message, or
2. The SMBALERT# signal goes active and the
SMB_SMI_EN bit is set and the SMBALERT_DIS bit is
cleared, or
3. The SMBus Slave receiving a Host Notify message and
the HOST_NOTIFY_INTREN and the SMB_SMI_EN bits
are set, or
4. The Intel
SMLINK_SLAVE_SMI command while in the S0 state.
sticky bit.
decoder.
PER_SMI_SEL bits. When the PERIODIC_EN bit is also
set, the Intel
that this is not a wake event.
- Any of the DEV[7:4]_TRAP_STS bits are set and the
corresponding DEV[7:4]_TRAP_EN bits are also set.
- Any of the DEVTRAP_STS bits are set and the
corresponding DEVTRAP_EN bits are also set.
®
®
6300ESB ICH detecting the
6300ESB ICH will generate an SMI#.
Power Well:
Description
Attribute:
Function:
Size:
st
timeout.
0
Read/Write
32-bit
Core
st
Order Number: 300641-004US
timeout.
Intel
®
6300ESB ICH—8
November 2007
Access
R/WC
R/WC
RO
RO
RO