NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 62

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 6.
Intel
DS
62
®
6300ESB I/O Controller Hub
PCI-X Interface Signals (Sheet 3 of 4)
PXPCLKO[4:
PXREQ[1:0]
PXGNT[1:0]
PXREQ[2]#
PXREQ[3]#
PXGNT[2]#
PXGNT[3]#
PXPCIRST#
PXPLOCK#
/ GPIO[1]
PXPCICLK
/GPIO[0]
PXRCOMP
PXPERR#
RASERR#
PXPCLKI
GPIO[16]
GPIO[17]
Name
0]
#
#
/
/
Type
I/O
I/O
I/O
OD
O
O
O
I
I
I
Parity Error: An external PCI-X device drives PXPERR# when it
receives data that has a parity error. The Intel
PXPERR# when it detects a parity error. The Intel
either generate an NMI# or SMI# upon detecting a parity error
(either detected internally or reported via the PXPERR# signal) when
serving as an initiator.
PCI-X Requests: Supports up to four masters on the PCI-X bus. The
Intel
its internal bus arbiter. The Intel
arbiter is an internal signal.
NOTE: When operating in PCI 64b/66MHz, only two external masters
PXREQ[2]# is muxed with GPIO[0]
PXREQ[3]# is muxed with GPIO[1]
PCI-X Grants: Supports up to 4 masters on the PCI-X bus.
PXGNT[2]# is muxed with GPIO[16]
PXGNT[3]# is muxed with GPIO[17]
NOTE: When operating in PCI 64b/66 MHz, only two external masters
PCI-X Clock In: This signal is connected to an output of the low
skew PCI clock buffer tree(PXPCLKO[4]. It is used by the PLL to
synchronize the PCI clock driven from PXPCLKO[4] to the clock used
for the internal PCI-X logic.
PCI-X Clock Output: 33/66 MHz clock for a PCI device. PXPCLKO[4]
is connected to the PXPCLKI input. In PCI 64/66 mode PXPCLKO(1:0)
are ensured to be driven.
PCI-X Clock: PXPCICLK is the clock for the internal PCI-X circuitry.
66Mhz primary input clock.
Impedance Compensation: Used to determine the impedance
between the Intel
RAS Error: This pin indicates that a RAS error has been logged. This
is an active low signal that is a logical OR of all the RAS error events.
If one of these errors is active, the pin is low. If none are active, then
the pin is high.
PCI/PCI-X Reset: The Intel
reset devices that reside on the PCI-X bus. The Intel
asserts PXPCIRST# during power-up and when S/W initiates a hard
reset sequence through the RC (CF9h) register. The Intel
ICH drives PXPCIRST# inactive a minimum of 1 ms after PWROK is
driven active. The Intel
minimum of 1 ms when initiated through the RC (CF9h) register.
NOTE: PXPCIRST# is in the Resume power plane. This signal also
PCI-X Lock: Indicates an exclusive bus operation and may require
multiple transactions to complete. The Intel
PXPLOCK# when it performs exclusive transactions on the PCI-X bus.
PLOCK# is ignored when PCI-X masters are granted the bus.
The Intel
upstream.
®
6300ESB ICH accepts four request inputs, PXREQ[3:0]# into
should be used,PXREQ0, PXREQ1.
should be used: PXGNT0, PXGNT1.
causes the legacy PCI bus and external PCI-X bus to reset
®
6300ESB ICH does not propagate locked transaction
®
6300ESB ICH and the PCI-X slots.
®
6300ESB ICH drives PXPCIRST# active a
Description
®
6300ESB ICH asserts PXPCIRST# to
®
6300ESB ICH request input to the
®
Order Number: 300641-004US
6300ESB ICH asserts
®
Intel
6300ESB ICH drives
®
6300ESB ICH may
®
®
6300ESB ICH
6300ESB ICH—3
November 2007
®
6300ESB