NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 353
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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8—Intel
Table 226. DMACH_MODE—DMA Channel Mode Register (Sheet 2 of 2)
8.2.8
Table 227. DMA Clear Byte Pointer Register
November 2007
Order Number: 300641-004US
Bits
Bits
Default Value:
Default Value:
3:2
1:0
7:0
I/O Address:
I/O Address:
4
Lockable:
Lockable:
®
Device:
Device:
6300ESB ICH
Autoinitialize Enable
DMA Channel Select
DMA Transfer Type
Clear Byte Pointer
DMA Clear Byte Pointer Register
31
Ch. #0-3 = 0Bh
Ch. #4-7 = D6h
0000 00xx
No
Name
31
Ch. #0-3 = 0Ch
Ch. #4-7 = D8h
xxxx xxxx
No
Name
0 = Autoinitialize feature is disabled and DMA transfers
1 = DMA restores the Base Address and Count registers to
These bits represent the direction of the DMA transfer. When
the channel is programmed for cascade mode, (bits[7:6] =
“11”) the transfer type is irrelevant.
00 = Verify - No I/O or memory strobes generated
01 = Write - Data transferred from the I/O devices to
memory
10 = Read - Data transferred from memory to the I/O device
11 = Illegal
These bits select the DMA Channel Mode Register that will be
written by bits [7:2].
00 = Channel 0 (4)
01 = Channel 1 (5)
10 = Channel 2 (6)
11 = Channel 3 (7)
No specific pattern. Command enabled with a write to the I/O
port address. Writing to this register initializes the byte
pointer flip/flop to a known state. It clears the internal latch
used to address the upper or lower byte of the 16-bit Address
and Word Count Registers. The latch is also cleared by part
reset and by the Master Clear command. This command
precedes the first access to a 16-bit DMA controller register.
The first access to a 16-bit register will then access the
significant byte, and the second access automatically
accesses the most significant byte.
terminate on a terminal count. A part reset or Master
Clear disables autoinitialization.
the current registers following a terminal count (TC).
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Write-Only
8-bit
Core
0
Write-Only
8-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
Access
WO
WO
WO
WO
353
DS
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