NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 136

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NHE6300ESB S L7XJ

Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet

Specifications of NHE6300ESB S L7XJ

Lead Free Status / RoHS Status
Compliant
5.8.1
5.8.2
Intel
DS
136
®
6300ESB I/O Controller Hub
Note: When the IDE primary and secondary controllers are configured for native IDE mode,
The Intel
the 15 ISA interrupts (IRQ0-1, 2-15), the four PCI interrupts, and the control signals
SMI# and IOCHK#. The serial IRQ protocol does not support the additional APIC
interrupts (20-23).
Serial interrupt information is transferred using three types of frames:
the only way to use the internal IRQ14 and IRQ15 connections to the Interrupt
Controllers is through the Serial Interrupt pin.
Start Frame
The serial IRQ protocol has two modes of operation which affect the start frame. These
two modes are: Continuous, where the Intel
generating the start frame; and Quiet, where a serial IRQ peripheral is responsible for
beginning the start frame.
The mode that must first be entered when enabling the serial IRQ protocol is
continuous mode. In this mode, the Intel
This start frame is 4, 6, or 8 PCI clocks wide based upon the Serial IRQ Control
Register, bits 1:0 at 64h in Device 31:Function 0 configuration space. This is a polling
mode.
When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the
SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a
peripheral drives the SERIRQ signal low. The Intel
and continues to drive it low for the remainder of the Start Frame. Since the first PCI
clock of the start frame was driven by the peripheral in this mode, the Intel
ICH will drive the SERIRQ line low for 1 PCI clock less than in continuous mode. This
mode of operation allows for a quiet, and therefore lower power, operation.
Data Frames
Once the Start frame has been initiated, all of the SERIRQ peripherals must start
counting frames based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has
exactly 3 phases of 1 clock each:
T - Turn-around Phase. Signal released
Start Frame: SERIRQ line driven low by the Intel
start of IRQ transmission
Data Frames: IRQ information transmitted by peripherals. The Intel
ICH will support 21 data frames.
Stop Frame: SERIRQ line driven low by the Intel
transmission and next mode of operation.
Sample Phase. During this phase, the SERIRQ device drives SERIRQ low when the
corresponding interrupt signal is low. When the corresponding interrupt is high, the
SERIRQ devices will tri-state the SERIRQ signal. The SERIRQ line will remain high
due to pull-up resistors (there is no internal pull-up resistor on this signal, an
external pull-up resistor is required). A low level during the IRQ0-1 and IRQ2-15
frames indicates that an active-high ISA interrupt is not being requested, but a low
level during the PCI INT[A:D], SMI#, and IOCHK# frame indicates that an active-
low interrupt is being requested.
Recovery Phase. During this phase, the device will drive the SERIRQ line high
when in the Sample Phase it was driven low. When it was not driven in the sample
phase, it will be tri-stated in this phase.
Turn-around Phase. The device will tri-state the SERIRQ line.
®
6300ESB ICH supports a message for 21 serial interrupts. These represent
®
6300ESB ICH will assert the start frame.
®
6300ESB ICH is solely responsible for
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6300ESB ICH senses the line low
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®
6300ESB ICH to indicate end of
6300ESB ICH to indicate the
Order Number: 300641-004US
Intel
®
®
6300ESB ICH—5
November 2007
6300ESB
®
6300ESB

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