NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 608

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

15.1.4
Intel
DS
608
63:3
2
1
0
Bits
Default Value:
®
Table 531. Offset 020-027h: General Interrupt Status Register
6300ESB I/O Controller Hub
Offset:
T02_INT_STS: Timer 2
T01_INT_STS: Timer 1
T00_INT_STS: Timer 0
Interrupt Active
Interrupt Active
Interrupt Active
Offset 020-027h: General Interrupt Status
Register
Reserved
020-027h
0000 0000 0000 0000h
Name
Reserved. These bits will return ’0’ when read.
Same functionality as Timer 0.
Same functionality as Timer 0.
The functionality of this bit depends on whether the edge or
level-triggered mode is used for this timer:
When set to level-triggered mode: This bit defaults to ‘0’.
This bit will be set by hardware when the corresponding timer
interrupt is active. Once the bit is set, it may be cleared by
software writing a ’1’ to the same bit position. Writes of ’0’ to
this bit will have no effect. For example, if the bit is already
set, a write of ’0’ will not clear the bit.
When set to edge-triggered mode: This bit should be
ignored by software. Software should always write ’0’ to this
bit.
NOTE: Defaults to ‘0’. In edge-triggered mode, this bit will
always read as ’0’ and writes will have no effect.
Description
Attribute:
Size:
Read/Write
64-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—15
November 2007
Access
R/W
R/W
R/W