NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 404

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.8.3.8
Table 291. GPE0_EN—General Purpose Event 0 Enables Register (Sheet 1 of 2)
Intel
DS
404
31:1
15:1
Bits
Default Value:
13
12
11
10
I/O Address:
6
4
9
8
7
6
5
®
6300ESB I/O Controller Hub
Lockable:
Note: This register is symmetrical to the General Purpose Event 0 Status Register. All the bits
Note: Usage: ACPI.
Device:
PME_B0_EN
TCOSCI_EN
GPE0_EN—General Purpose Event 0 Enables Register
in this register should be cleared to 0 based on a Power Button Override. The resume
well bits are all cleared by RSMRST#. The RTC well bits are cleared by RTCRST#.
Reserved
Reserved
Reserved
Reserved
Reserved
AC97_EN
GPIn_EN
PME_EN
31
PMBASE + 2Ch
(ACPI GPE0_BLK + 4)
00000000h
No
Name
RI_EN
These bits enable the corresponding GPI[n]_STS bits being
set to cause a SCI, and/or wake event. These bits are cleared
by RSMRST#.
Reserved.
Enables the setting of the PME_B0_STS bit to generate a
wake event and/or an SCI or SMI#. PME_B0_STS may be a
wake event from the S1-S4 states, or from S5 (when entered
through SLP_TYP and SLP_EN) or power failure, but not
Power Button Override. This bit defaults to 0. It is only
cleared by Software or RTCRST#. It is not cleared by CF9h
writes.
Reserved.
This bit defaults to 0. It is only cleared by Software or
RTCRST#. It is not cleared by CF9h writes.
0 = Disable.
1 = Enables the setting of the PME_STS to generate a wake
Reserved.
Reserved.
The value of this bit will be maintained through a G3 state
and is not affected by a hard reset caused by a CF9h write.
0 = Disable.
1 = Enables the setting of the RI_STS to generate a wake
Reserved.
0 = Disable.
1 = Enables the setting of the TCOSCI_STS to generate an
0 = Disable.
1 = Enables the setting of the AC97_STS to generate a wake
event and/or an SCI. PME# may be a wake event from
the S1 - S4 state or from S5 (when entered through
SLP_EN or power failure, but not power button override).
event.
SCI.
event.
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
32-bit
Bits 0-7, 12, 16-31 Resume,
Bits 8-11, 13 RTC
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
R/W
R/W
R/W
R/W
R/W