NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 553

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

13—Intel
November 2007
Order Number: 300641-004US
10:9
Bits
Default Value:
3:0
15
14
13
12
11
8
7
6
5
4
Table 463. Offset 06 - 07h: PCISTS—PCI Device Status Register (Audio—
Lockable:
Device:
®
DEVSEL# Timing Status
Offset:
SERR# Status (SERRS)
Capabilities List Exists
Signaled Target-Abort
Detected Parity Error
Data Parity Detected
6300ESB ICH
Master-Abort Status
Fast Back to back
66 MHz Capable
Capable (FBC)
Status (STA)
D31:F5)
Reserved
Reserved
Reserved
(CLIST)
(DEVT)
31
06-07h
0290h
No
Name
(MAS)
(DPD)
(DPE)
Not implemented. Hardwired to ‘0’.
Not implemented. Hardwired to ‘0’.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Bus Master AC '97 2.2 interface function, as a master,
Reserved. Will always read as ‘0’.
Not implemented. Hardwired to ‘0’.
This 2-bit field reflects the Intel
timing when performing a positive decode.
01b = Medium timing.
Hardwired to ‘01’.
Not implemented. Hardwired to ‘0’.
Hardwired to ‘1’. This bit indicates that the Intel
ICH as a target is capable of fast back-to-back transactions.
Reserved. Hardwired to ‘0’.
Hardwired to ‘0’.
Indicates that the controller contains a capabilities pointer
list. The first item is pointed to by looking at configuration
offset 34h.
Reserved.
generates a master abort.
Power Well:
Description
Attribute:
Function:
Size:
®
6300ESB ICH's DEVSEL#
5
Read/Write Clear
16-bit
Core
®
Intel
6300ESB
®
6300ESB I/O Controller Hub
Access
R/WC
RO
553
DS