NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 603

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

14—Intel
November 2007
Order Number: 300641-004US
Bits
Default Value:
17
16
15
14
13
12
11
10
I/O Address:
9
8
Table 526. GLOB_STA—Global Status Register (Sheet 2 of 3)
Lockable:
Device:
®
Read Completion Status
AC_SDIN1 Codec Ready
AC_SDIN0 Codec Ready
6300ESB ICH
AC_SDIN1 Resume
AC_SDIN0 Resume
Interrupt (S1RI)
Interrupt (S0RI)
Bit 3 of slot 12
Bit 2 of slot 12
Bit 1 of slot 12
(S1CR)
(S0CR)
29
MBAR + 40h
00300000h
No
Name
(RCS)
MD3
AD3
Power down semaphore for Modem. This bit exists in the
suspend well and maintains context across power states
(except G3). The bit has no hardware function. It is used by
software in conjunction with the AD3 bit to coordinate the
entry of the two codecs into D3 state.
This bit is not affected by D3
Power down semaphore for Audio. This bit exists in the
suspend well and maintains context across power states
(except G3). The bit has no hardware function. It is used by
software in conjunction with the MD3 bit to coordinate the
entry of the two codecs into D3 state.
This bit is not affected by D3
This bit indicates the status of codec read completions.
0 = A codec read completes normally.
1 = A codec read results in a time-out. The bit remains set
This bit is not affected by D3
Display bit 3 of the most recent slot 12.
Display bit 2 of the most recent slot 12.
Display bit 1 of the most recent slot 12.
This bit indicates that a resume event occurred on
AC_SDIN[1].
0 = Cleared by writing a ’1’ to this bit position.
1 = Resume event occurred.
This bit is not affected by D3
This bit indicates that a resume event occurred on
AC_SDIN[0].
0 = Cleared by writing a ’1’ to this bit position.
1 = Resume event occurred.
This bit is not affected by D3
Reflects the state of the codec ready bit in AC_SDIN[1]. Bus
masters ignore the condition of the codec ready bits, so
software must check this bit before starting the bus masters.
Once the codec is “ready”, it must never go “not ready”
spontaneously.
0 = Not Ready.
1 = Ready.
Reflects the state of the codec ready bit in AC_SDIN [0]. Bus
masters ignore the condition of the codec ready bits, so
software must check this bit before starting the bus masters.
Once the codec is “ready”, it must never go “not ready”
spontaneously.
0 = Not Ready.
1 = Ready.
until being cleared by software writing a “1” to the bit
location.
Power Well:
Description
Attribute:
Function:
HOT
HOT
HOT
HOT
HOT
Size:
to D0 Reset.
to D0 Reset.
to D0 Reset.
to D0 Reset.
to D0 Reset.
5
Read-Only, Read/Write, Read/Write Clear
32-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
R/WC
R/WC
R/WC
R/W
R/W
RO
RO
RO
RO
RO
603
DS