NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 326

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 200. Offset 8Ah: D31_ERR_STS—Device 31 Error Status Register (LPC I/F—
8.1.21
Table 201. Offset 90h - 91h: PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—
Intel
DS
326
15:1
13:1
11:1
Bits
Bits
Default Value:
Default Value:
7:3
9:8
7:6
2
1
0
4
2
0
®
6300ESB I/O Controller Hub
Lockable:
Lockable:
Note: Since there is no ISA bus, the default is for DMA to be disabled. BIOS must set
Device:
to Received Target Abort
Device:
SERR_RTA: SERR# Due
Offset:
SERR_DTT: SERR# Due
Offset:
to Delayed Transaction
Channel 7 Select
Channel 6 Select
Channel 5 Select
Channel 3 Select
D31:F0)
Offset 90h - 91h: PCI_DMA_CFG—PCI DMA
Configuration (LPC I/F—D31:F0)
particular channels for LPC DMA. When ISA is present (through MoonISA), channels not
assigned to LPC should be assigned as Disabled.
D31:F0) (Sheet 1 of 2)
Reserved
Reserved
Reserved
Timeout
31
8Ah
00h
No
Name
31
90h-91h
0000h
No
Name
Reserved.
0 = Software clears this bit by writing a 1 to the bit location.
1 = The Intel
0 = Software clears this bit by writing a 1 to the bit location.
1 = When a PCI master does not return for the data within 1
Reserved.
00 = Reserved
01 = Reserved
10 = Reserved
11 = LPC I/F DMA
Same bit decode as for Channel 7.
Same bit decode as for Channel 7.
Reserved.
Same bit decode as for Channel 7.
target abort. When SERR_EN, the Intel
will also generate an SERR# when SERR_RTA is set.
ms of the cycle’s completion, the Intel
clears the delayed transaction and sets this bit. When
both SERR_DTT_EN and SERR_EN are set, then Intel
6300ESB ICH will also generate an SERR# when
SERR_DTT is set.
®
6300ESB ICH sets this bit when it receives a
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read/Write Clear
8-bit
Core
0
Read/Write
16-bit
Core
®
®
6300ESB ICH
6300ESB ICH
Order Number: 300641-004US
Intel
®
®
6300ESB ICH—8
November 2007
Access
Access
R/WC
R/WC
R/W
R/W
R/W
R/W