NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 178

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.13.2
5.13.3
5.13.4
5.14
5.14.1
Intel
DS
178
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6300ESB I/O Controller Hub
Note: A bit may be routed to either an SMI# or an SCI, but not both.
Note: GPIs that are in the core well are not capable of waking the system from sleep states
Power Wells
Some GPIOs exist in the resume power plane. Care must be taken to make sure GPIO
signals are not driven high into powered-down planes.
Some Intel
core well. When these GPIOs are outputs, there is a danger that a loss of core power
(PWROK low) or a Power Button Override event will result in the Intel
driving a pin to a logic ‘1’ to another device that is powered down.
SMI# and SCI Routing
The routing bits for GPIO[0:15] allow an input to be routed to SMI# or SCI, or neither.
See
Triggering
GPIO[0:15] have “sticky” bits on the input. See
register. As long as the signal goes active for at least 2 clocks, the Intel
will keep the sticky status bit active. The active level (high or low) can be selected via
the GP_INV register.
If the system is in an S0 or S1-D state, the GPI are sampled at 33 MHz, so the signal only needs to
be active for about 60 ns to be latched. In the S3-S5 states, the GPI are sampled at 32.768 KHz, and
thus must be active for at least 61 microseconds to be latched.
where the core well is not powered.
If the input signal is still active when the latch is cleared, it will again be set (another
edge is not required). This makes these signals ìlevelî triggered inputs.
IDE Controller (D31:F1)
Overview
The Intel
and Secondary) that may be independently enabled, tri-stated or driven low.
The Intel
IDE interface. In native mode, the IDE controller is a fully PCI compliant software
interface and does not use any legacy I/O or interrupt resources.
The IDE interfaces of the Intel
transfers:
Programmed I/O (PIO): Processor is in control of the data transfer.
8237 style DMA: DMA protocol that resembles the DMA on the ISA bus, although it
does not use the 8237 in the Intel
from moving data. This allows higher transfer rate of up to 16 Mbytes/s.
Section 8.8.3.3
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6300ESB ICH IDE controller features two sets of interface signals (Primary
6300ESB ICH IDE controller supports both legacy mode and native mode
6300ESB ICH GPIOs may be connected to pins on devices that exist in the
for the routing register
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6300ESB ICH may support several types of data
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6300ESB ICH. This protocol off loads the processor
Section 8.8.3.7
Order Number: 300641-004US
for the GPE0_STS
Intel
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6300ESB ICH
6300ESB ICH—5
6300ESB ICH
November 2007