NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 111
NHE6300ESB S L7XJ
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NHE6300ESB S L7XJ
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Intel
Datasheet
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5—Intel
Table 40.
5.5.5
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Only two conventions need to be observed when programming the counters. First, for
each counter, the control word must be written before the initial count is written.
Second, the initial count must follow the count format specified in the control word
(least significant byte only, most significant byte only, or least significant byte and then
most significant byte).
A new initial count may be written to a counter at any time without affecting the
counter's programmed mode. Counting will be affected as described in the mode
definitions. The new count must follow the programmed count format.
When a counter is programmed to read/write two-byte counts, the following precaution
applies: A program must not transfer control between writing the first and second byte
to another routine which also writes into that same counter. Otherwise, the counter will
be loaded with an incorrect count.
The Control Word Register at port 43h controls the operation of all three counters.
Several commands are available:
Table 40
Counter Operating Modes
Reading from the Interval Timer
It is often desirable to read the value of a counter without disturbing the count in
progress. There are three methods for reading the counters: a simple read operation,
counter Latch command, and the Read-Back command. Each is explained below.
1. Write a control word to select a counter.
2. Write an initial count for that counter.
3. Load the least and/or most significant bytes (as required by Control Word bits 5, 4)
4. Repeat with other counters.
•
•
•
Mode
of the 16-bit counter. See
Control Word Command. Specifies which counter to read or write, the operating
mode, and the count format (binary or BCD).
Counter Latch Command. Latches the current count so that it may be read by
the system. The countdown process continues.
Read Back Command. Reads the count value, programmed mode, the current
state of the OUT pins, and the state of the Null Count Flag of the selected counter.
0
1
2
3
4
5
lists the six operating modes for the interval counters.
Out signal on end of count (=0)
Hardware retriggerable one-shot
Rate generator (divide by n
counter)
Square wave output
Software triggered strobe
Hardware triggered strobe
Function
Section 8.3, “Timer I/O Registers”
Output is ‘0’. When count goes to 0, output goes
to ‘1’ and stays at ‘1’ until counter is
reprogrammed.
Output is ‘0’. When count goes to 0, output goes
to ‘1’ for one clock period.
Output is ‘1’. Output goes to ‘0’ for one clock
time, then back to ‘1’ and counter is reloaded.
Output is ‘1’. Output goes to ‘0’ when counter rolls
over, and counter is reloaded. Output goes to ‘1’
when counter rolls over, and counter is reloaded,
etc.
Output is ‘1’. Output goes to ‘0’ when count
expires for one clock period.
Output is ‘1’. Output goes to ‘0’ when count
expires for one clock period.
Description
Intel
®
for more information.
6300ESB I/O Controller Hub
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