NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 420

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 306. TCO1_STS—TCO1 Status Register (Sheet 2 of 2)
Intel
DS
420
Bits
Default Value:
6:4
I/O Address:
7
3
2
1
0
®
6300ESB I/O Controller Hub
Lockable:
Device:
NEWCENTURY_STS
NMI2SMI_STS
TCO_INT_STS
SW_TCO_SMI
Reserved
TIMEOUT
31
TCOBASE +04h
0000h
No
Name
This bit is in the RTC well.
0 = Cleared by writing a 1 to the bit position or by RTCRST#
1 = This bit is set when the Year byte (RTC I/O space, index
Note that the NEWCENTURY_STS bit is not valid when the
RTC battery is first installed (or when RTC power has not been
maintained). Software may determine when RTC power has
not been maintained by checking the RTC_PWR_STS bit, or
by other means (such as a checksum on RTC RAM). When
RTC power is determined to have not been maintained, BIOS
should set the time to a legal value and then clear the
NEWCENTURY_STS bit.
The NEWCENTURY_STS bit may take up to 3 RTC clocks for
the bit to be cleared after a “1” is written to the bit to clear it.
After writing a “1” to this bit, software should not exit the SMI
handler until verifying that the bit has actually been cleared.
This will ensure that the SMI is not re-entered.
Reserved.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by the Intel
0 = Software clears this bit by writing a 1 to the bit position.
1 = SMI handler caused the interrupt by writing to the
0 = Software clears this bit by writing a 1 to the bit position.
1 = Software caused an SMI# by writing to the TCO_DAT_IN
0 = Cleared by clearing the associated NMI status bit.
1 = Set by the Intel
going active.
offset 09h) rolls over from 99 to 00. Setting this bit will
cause an SMI# (but not a wake event).
was caused by the TCO timer reaching 0.
TCO_DAT_OUT register.
register.
because an event occurred that would otherwise have
caused an NMI (because NMI2SMI_EN is set).
®
®
6300ESB ICH to indicate that the SMI
6300ESB ICH when an SMI# occurs
Power Well:
Description
Attribute:
Function:
Size:
0
Read-Only, Read/Write Clear
16-bit
Core (Except bit 7, in RTC)
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/WC
R/WC
R/WC
R/WC
RO