NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 63

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

3—Intel
Table 6.
November 2007
Order Number: 300641-004US
®
6300ESB ICH
PCI-X Interface Signals (Sheet 4 of 4)
PXPCIXCAP
PCIXSBRST
PXREQ64#
PXACK64#
PXM66EN
PXSERR#
PXPAR64
Name
PME#
#
Type
I/OD
I/OD
I/O
I/O
I/O
O
I
I
System Error: PXSERR# may be pulsed active by any PC-X device
that detects a system error condition except Intel
The Intel
conditionally forwards it to the Hub Interface. Upon sampling
PXSERR# active, the Intel
generate an NMI or SMI#.
PCI Power Management Event: PCI-X peripherals drive PME# to
wake the system from low-power states S1–S5. PME# assertion may
also be enabled to generate a SCI from the S0 state. In some cases
the Intel
wake event. The Intel
will be pulled up to VccSus3_3 by an internal pull-up resistor.
NOTE: PME# is in the Resume power plane and has an internal pull-
PME# control logic is in the primary PCI bus logic and not the PCI-X
bridge
66MHz Enable: This input signal from the PCI-X Bus indicates the
speed of the PCI-X Bus. When it is high, the Bus speed is 66 MHz and
when it is low, the bus speed is 33 MHz. This signal will be used to
generate appropriate clock (33 or 66MHz) on the PCI-X Bus.
PCI-X Capable: Indicates whether all devices on the PCI-X bus are
PCI-X devices, so that the Intel
mode
PCI-X interface upper 32-bits parity: This carries the even parity
of the 36 bits of PXAD[63:32] and PXC/BE#[7:4] for both address
and data phases.
When not driven, PXPAR64 is pulled up to a valid logic level through
external resistors
PCI-X interface request 64-bit transfer: This is asserted by the
initiator to indicate that the initiator is requesting a 64-bit data
transfer. It has the same timing as PXFRAME#. When the Intel
6300ESB ICH is the initiator, this signal is an output. When the Intel
6300ESB ICH is the target this signal is an input
PCI-X interface acknowledge 64-bit transfer: This is asserted by
the target only when PXREQ64# is asserted by the initiator, to
indicate the target’s ability to transfer data using 64 bits. It has the
same timing as PXDEVSEL#
PCI-X Secondary Bus Reset: The Intel
PCIXSBRST# to reset devices that reside on the PCI-X bus. The
Intel
asserted or when SBR bit is set.
®
6300ESB ICH asserts PCIXSBRST# when the PXPCIRST# pin is
up resistor.
®
®
6300ESB ICH may drive PME# active due to an internal
6300ESB ICH samples PXSERR# as an input and
®
6300ESB ICH will not drive PME# high, but it
®
Description
6300ESB ICH may be programmed to
®
6300ESB ICH may switch into PCI-X
Intel
®
6300ESB ICH asserts
®
6300ESB I/O Controller Hub
®
6300ESB ICH.
®
®
DS
63