NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 396

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.8.3.2
Table 285. PM1_EN—Power Management 1 Enable Register
Intel
DS
396
15:1
Bits
Default Value:
7:6
4:1
10
I/O Address:
1
9
8
5
0
®
6300ESB I/O Controller Hub
Lockable:
Note: Usage: ACPI or Legacy.
Device:
GBL_EN: Global Enable
RTC_EN: RTC Event
Overflow Interrupt
TMROF_EN. Timer
PWRBTN_EN
PM1_EN—Power Management 1 Enable Register
Reserved
Reserved
Reserved
Reserved
Enable
Enable
31
PMBASE + 02h
(ACPI PM1a_EVT_BLK +
2)
0000h
No
Name
Reserved.
This bit is in the RTC well to allow an RTC event to wake after
a power failure. This bit is not cleared by any reset other than
RTCRST# or a Power Button Override event.
0 = No SCI (or SMI#) or wake event is generated then
1 = An SCI (or SMI#) and a wake event will occur when this
Reserved.
This bit is the power button enable. It works in conjunction
with the SCI_EN bit:
PWRBTN_EN
PWRBTN_EN has no effect on the PWRBTN_STS bit being set
by the assertion of the power button. The Power Button is
always enabled as a Wake event.
Reserved.
When both the GBL_EN and the GBL_STS are set, an SCI is
raised.
Disable.
Enable SCI on GBL_STS going active.
Reserved.
Works in conjunction with the SCI_EN bit as described below:
TMROF_EN
S5,
wake
wake
0
1
1
0
1
1
RTC_STS goes active.
bit is set and the RTC_STS bit goes active.
SCI_EN Effect when PWRBTN_STS is set
SCI_EN Effect when TMROF_STS is set
x
0
1
1
x
0
Power Well:
No SMI# or SCI
SMI#
SCI
No SMI# or SC. If system was in S1-
no wake event
SMI# If system was in S1-S5, then a
vent occurs before the SMI#
SCI If system was in S1-S5, then a
vent occurs before the SMI#
Description
Attribute:
Function:
Size:
0
Read/Write
16-bit
Bits 0-7: Core
Bits 8-9, 11-15: Resume
Bit 10: RTC
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
R/W
R/W