NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 755

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

20—Intel
20.1.25 Offset 70 - 71h: PID—PCI Power Management
20.1.26 Offset 72 - 73h: PC—PCI Power Management
November 2007
Order Number: 300641-004US
15:8
15:1
Bits
Bits
Bits
Default Value:
Default Value:
Default Value:
7:0
10
2
1
0
1
9
Table 683. Offset 54h: IDE_CONFIG—IDE I/O Configuration Register (SATA–
Table 684. Offset 70 - 71h: PID—PCI Power Management Capability ID (SATA–
Table 685. Offset 72 - 73h: PC—PCI Power Management Capabilities (SATA–
Device:
Device:
Device:
®
Offset:
SCBO: Secondary Drive
Offset:
Offset:
Next Capability (NEXT)
PCB1: Primary Drive 1
PCB0: Primary Drive 0
6300ESB ICH
Cap ID (CID)
PME_Support
0 Base Clock
D2_Support
D1_Support
Base Clock
Base Clock
D31:F2) (Sheet 2 of 2)
Capability ID (SATA–D31:F2)
D31:F2)
Capabilities (SATA–D31:F2)
D31:F2)
31
54h
00h
Name
31
70-71h
0001h
Name
31
72-73h
0002
Name
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
Indicates that this pointer is a PCI power management.
Indicates PME# cannot be generated form the SATA host
controller. When in low power state, resume events are not
allowed.
The D2 state is not supported
The D1 state is not supported
Indicates that this is the last item in the list
Description
Description
Description
Attribute:
Attribute:
Attribute:
Function:
Function:
Function:
Size:
Size:
Size:
2
Read-Write
32-bit
2
Read-Only
16-bit
2
Read-Only
16-bit
Intel
®
6300ESB I/O Controller Hub
Access
Access
Access
R/W
R/W
R/W
755
DS