NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 697
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
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Specifications of NHE6300ESB S L7XJ
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18—Intel
Table 627. Split Terminations of Completion Required Cycles to PCI-X (Sheet 2 of
18.9.3
Table 628. Hub Interface Response to PCI-X Split Completion Terminations of
November 2007
Order Number: 300641-004US
®
6300ESB ICH
2)
PCI-X Split Completions
The following table indicates what the Intel
split completion to PCI-X from a normal Hub Interface completion, and receives an
immediate response indicating some kind of error.
Completion Required Cycles
Hub Interface Action on Immediate Responses to
Write Data Parity Error
Device Specific
Reserved/Illegal
Successful
Master Abort
Target Abort
† In this case, the assertion of SERR# and setting of the Signaled System Error bit only occur when the
Split Completion Termination
SERR# Enabled in the primary command register is set.
Termination
PCI-X Split
Class
2
2
Message
Others
Index
8Xh
None
Assert SERR#
Assert SERR#
01h
Target Abort
Target Abort
Target Abort
Hub Interface
Action
Completion
®
6300ESB ICH does when it is returning a
†
†
Master Data Parity Error (Sec)
Signaled Target Abort (Pri)
Signaled Target Abort (Pri)
Signaled Target Abort (Pri)
None
Received Master Abort (Sec)
Split Completion Discarded (Sec)
Signaled System Error (Pri)
Received Target Abort (Sec)
Split Completion Discarded (Sec)
Signaled System Error (Pri)
Status Register Bits Set
Intel
Status Register Bits
®
6300ESB I/O Controller Hub
†
†
697
DS
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