NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 153

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.11.6.1 Throttling Using STPCLK#
5.11.6.2 Transition Rules among S0/Cx and Throttling States
November 2007
Order Number: 300641-004US
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6300ESB ICH
The break event associated with this new mechanism does not need to set any
particular status bit, since the pending interrupt will be serviced by the processor after
returning to the C0 state.
Throttling is used to lower power consumption or reduce heat. The Intel
asserts STPCLK# to throttle the processor clock and the processor appears to
temporarily enter a C2 state. After a programmable time, the Intel
deasserts STPCLK# and the processor appears to return to the C0 state. This allows the
processor to operate at reduced average power, with a corresponding decrease in
performance. Two methods are included to start throttling:
Throttling due to the THRM# signal has higher priority than the software initiated
throttling.
Throttling does not occur when the system is in a C2 state, even when Thermal
override occurs.
The following priority rules and assumptions apply among the various S0/Cx and
throttling states:
5. The Intel
1. Software enables a timer with a programmable duty cycle. The duty cycle is set by
2. A Thermal Override condition (THRM# signal active for >2 seconds) occurs that
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deasserting STPCLK# and then starts using the FERR# signal for an indication of a
floating point error. The maximum time that the Intel
bounded such that it must have a chance to look at the FERR# signal before
reasserting STPCLK#. Based on current implementation, that maximum time would
be 240 ns (8 PCI clocks). Since the processor has 120-210 ns to revert to the
proper FERR# function, there are 60-30 ns of margin inherent in the timings.
the THTL_DTY field and the throttling is enabled using the THTL_EN field. This is
known as Manual Throttling. The period is fixed to be in the non-audible range, due
to the nature of switching power supplies.
unconditionally forces throttling, independent of the THTL_EN bit. The throttling
due to Thermal Override has a separate duty cycle (THRM_DTY) which may vary by
field and system. The Thermal Override condition will end when THRM# goes
inactive.
Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This
is because the processor may only perform one register access at a time and Sleep
states have higher priority than thermal throttling.
When the SLP_EN bit is set (system going to a sleep state (S1–S5), the THTL_EN
bit may be internally treated as being disabled (no throttling while going to sleep
state). Note that thermal throttling (based on THRM# signal) cannot be disabled in
an S0 state. However, once the SLP_EN bit is set, the thermal throttling is shut off
(since STPCLK# will be active in S1–S5 states).
When the THTL_EN bit is set, and a Level 2 read then occurs, the system should
immediately go and stay in a C2 state until a break event occurs. A Level 2 read
has higher priority than the software initiated throttling or thermal throttling.
When Thermal Override is causing throttling, and a Level 2 read then occurs, the
system will stay in a C2 state until a break event occurs. A Level 2 read has higher
priority than the Thermal Override.
After an exit from a C2 state (due to a break event), and when the THTL_EN bit is
still set, or when a Thermal Override is still occurring, the system will continue to
throttle STPCLK#. Depending on the time of break event, the first transition on
STPCLK# active may be delayed by up to one THRM period (1024 PCI clocks=30.72
microseconds).
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6300ESB ICH waits at least 180 ns to 8 PCI clocks (240 ns) after
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6300ESB ICH may wait is
Intel
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