NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 196

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.17
5.17.1
5.17.2
5.17.2.1 Frame List Pointer
Table 86.
Intel
DS
196
®
6300ESB I/O Controller Hub
When a 32-bit processor does not want to halt the timer, it may use the 64-bit timer as
a 32-bit timer by setting the TIMERn_32MODE_CNF bit. This will cause the timer to
behave as a 32-bit timer. The upper 32 bits will always be 0.
USB UHCI Controllers (D29:F0 and F1)
Overview
The Intel
includes a root hub with two separate USB ports each, for a total of four USB ports. The
Intel
Interface (UHCI) Specification, Rev 1.1.
Overcurrent detection on all four USB ports is supported. The overcurrent inputs are
5V-tolerant and may be used as GPIs when not needed.
The Intel
standard PCI devices to improve arbitration latency.
The USB UHCI controllers use the Analog Front End (AFE) embedded cell that allows
support for USB High-speed signaling rates instead of USB I/O buffers.
Data Structures in Main Memory
This section describes the details of the data structures used to communicate control,
status, and data between software and the Intel
Descriptors, and Queue Heads. Frame Lists are aligned on 4-Kbyte boundaries. Transfer
Descriptors and Queue Heads are aligned on 16-byte boundaries.
The frame list pointer contains a link pointer to the first data object to be processed in
the frame, as well as the control bits defined in
Frame List Pointer Bit Description
31:4
3:2
Bit
1
0
®
6300ESB ICH Host Controllers support the standard Universal Host Controller
Frame List Pointer (FLP): This field contains the address of the first data object to be
processed in the frame and corresponds to memory address signals [31:4], respectively.
Reserved. These bits must be written as zero.
QH/TD Select (Q): This bit indicates to the hardware whether the item referenced by
the link pointer is a TD (Transfer Descriptor) or a QH (Queue Head). This allows the
Intel
fetched.
1 = QH
0 = TD
Terminate (T): This bit indicates to the Intel
this frame has valid entries in it.
1 = Empty Frame (pointer is invalid).
0 = Pointer is valid (points to a QH or TD).
®
®
6300ESB ICH contains two USB UHCI Host Controllers. Each Host Controller
6300ESB ICH’s USB UHCI controllers are arbitrated differently from
®
6300ESB ICH to perform the proper type of processing on the item after it is
Description
Table
®
®
6300ESB ICH whether the schedule for
6300ESB ICH: Frame Lists, Transfer
86.
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007