NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 95

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
Figure 8.
5.1.5
November 2007
Order Number: 300641-004US
®
Note: The Intel
Note: When NMIs are enabled, and parity error checking on PCI is also enabled, then parity
6300ESB ICH
NMI# Generation Logic
Parity Error Detection
The Intel
The Intel
routed to SMI#) based on detecting a parity error. The conceptual logic diagram in
Figure 8
with their respective enable bits, status bits, and the results.
device (PERR#) across the P2P bridge.
errors will cause an NMI. Some operating systems will not attempt to recover from this
NMI, since it considers the detection of a PCI error to be a catastrophic event.
S_SSE for PCI-X
Pre-latch S_SSE
Pre-latch P_SSE
South PCI Parity Error Detected
HubLink Parity Error Detected
USBe_SSE
Pre-latch
D30_S_PER (D30:3Eh.0)
D30_P_PER (D30:04h.6)
PCI Parity Error Detected
D31_S_PER (D31:04h.6)
®
®
details all the parity errors that the Intel
®
6300ESB ICH may detect and report different parity errors in the system.
6300ESB ICH may be programmed to cause an NMI (or SMI# when NMI is
6300ESB ICH does not escalate a data parity mismatch reported by a PCI
IOCHK from SERIRQ Logic
D30_SDPD (D30:1Eh:8)
PCI-X PERR_PIN
PCI_SERR_STS
(Port 61.2)
(D28:3E.0)
OR
D31_DPT (D31:06h.8)
D29:F7:06h.14
Port 61.3
AND
AND
AND
AND
AND
TCONMI_STS
PUSERR_NMI
AND
(D30:06h:8)
D30_PDPD
SERR_NMI_STS
(Port 61.7)
IOCHK_NMI_STS
OR
(Port 61.6)
®
6300ESB ICH may detect, along
Port 70:7
OR
Intel
®
6300ESB I/O Controller Hub
AND
To NMI#
Output and
Gating Logic
A9644-01
DS
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