NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 702
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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18.13.3 Active Master Clock Counts
Intel
DS
702
®
6300ESB I/O Controller Hub
References to signal timings are stated from the point of view of the bus itself. Internal
register timings of the individual devices are not considered.
One Megabyte =10
This section specifies clock counts for general bus timings and first word latencies for
read requests. Bus timings should be consistent regardless of other system activity.
First word latency specifications only apply in situations where contention for system
resources does not present a performance bottleneck.
First word latency is measured as the number of clocks from the initial assertion of
PXFRAME# (this is clock 0) to the first clock on which valid data is returned in response
to the request.
6
Bytes rather than 2
20
Bytes.
Order Number: 300641-004US
Intel
®
6300ESB ICH—18
November 2007
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