NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 401
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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8—Intel
Table 290. GPE0_STS—General Purpose Event 0 Status Register (Sheet 1 of 3)
November 2007
Order Number: 300641-004US
31:1
15:1
Bits
Default Value:
13
12
I/O Address:
6
4
Lockable:
®
Device:
6300ESB ICH
PME_B0_STS
GPIn_STS
Reserved
Reserved
31
PMBASE + 28h
(ACPI PGPE0_BLK)
00000000h
No
Name
These bits are set any time the corresponding GPIO is set up
as an input and the corresponding GPIO signal is high (or low
when the corresponding GP_INV bit is set). When the
corresponding enable bit is set in the GPE0_EN register, then
the GPI[n]_STS bit is set:
NOTE: These bits are sticky and are cleared by writing a 1
Corresponding bits and GPIOs
Bit #
16
17
18
19
20
21
22
23
Reserved.
This bit will be set to 1 by the Intel
internal device on bus 0 asserts the equivalent of the PME#
signal. Additionally, when the PME_B0_EN bit is set, and the
system is in an S0 state, the setting of the PME_B0_STS bit
will generate an SCI (or SMI# when SCI_EN is not set). When
the PME_B0_STS bit is set, and the system is in an S1-S4
state (or S5 state due to SLP_TYP and SLP_EN), the setting of
the PME_B0_STS bit will generate a wake event, and an SCI
(or SMI# when SCI_EN is not set) will be generated. When
the system is in an S5 state due to power button override,
the PME_B0_STS bit will not cause a wake event or SCI.
The default for this bit is 0. Writing a 1 to this bit position
clears this bit.
Reserved.
• When the system is in an S1-S5 state, the event will also
• When the system is in an S0 state (or upon waking back
wake the system.
to an S0 state), a SCI will be caused depending on the
GPI_ROUT bits for the corresponding GPI.
back to this bit position.
GPI[n]Bit #
0
1
2
3
4
5
6
7
Power Well:
Description
Attribute:
Function:
GPI[n]
25
26
27
28
29
30
31
24
Size:
®
0
Read/Write Clear
32-bit
Resume
6300ESB ICH when any
na
na
12
13
na
na
11
8
Intel
®
6300ESB I/O Controller Hub
Access
R/WC
R/WC
401
DS
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