NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 620

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

16.4.6
Table 541. Offset 06h - 07h: DS—Device Status Register
Intel
DS
620
10:9
Bits
Default Value:
4:0
15
14
13
12
11
8
7
6
5
®
6300ESB I/O Controller Hub
Lockable:
Device:
DEVT - DEVSEL# Timing
Offset:
SSE - Signaled System
RMA - Received Master
STA - Signaled Target-
RTA - Received Target
DPE - Detected Parity
UDF - User Definable
Fast Back-to-Back
Data Parity Error
66 MHz Capable
Abort Status
Offset 06h - 07h: DS—Device Status Register
Reserved
Detected
Features
Capable
Status
29
06h - 07h
0280h
No
Name
Abort
Abort
Error
Error
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
This bit is set when the function is targeted with a transaction
that the Intel
Software resets STA to ’0’ by writing a ’1’ to this bit location.
This 2-bit field defines the timing for DEVSEL# assertion.
These read only bits indicate Intel
timing when performing a positive decode.
The Intel
time.
Reserved as ‘0’.
Reserved as ‘1’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved.
®
6300ESB ICH generates DEVSEL# with medium
®
6300ESB ICH terminates with a target abort.
Power Well:
Description
Attribute:
Function:
Size:
®
6300ESB ICH’s DEVSEL#
4
Read/Write Clear
16-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—16
November 2007
Access
R/WC
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO