NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 562

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

13.1.20 Offset 41h: CFG—Configuration Register (Audio—
13.1.21 Offset 50h: PID—PCI Power Management
Intel
DS
562
15:8
Bits
Bits
Default Value:
Default Value:
7:1
7:0
0
®
Table 479. Offset 41h: CFG—Configuration Register (Audio—D31:F5)
Table 480. Offset 50h: PID—PCI Power Management Capability ID Register
6300ESB I/O Controller Hub
Lockable:
Lockable:
Note: This register is used to specify the ID for the secondary and tertiary codecs for I/O
I/O Space Enable (IOSE)
Device:
Device:
Offset:
Offset:
Next Capability (NEXT)
Cap ID (CAP)
D31:F5)
accesses. This register is not affected by the D3
Capability ID Register (Audio—D31:F5)
(Audio—D31:F5)
Reserved
31
41h
00h
No
Name
31
50h
0001h
No
Name
Reserved.
When cleared, the IOSE bit at offset 04h and the I/O space
BARs at offset 10h and 14h become read-only registers. This
is the default state for the I/O BARs. BIOS must explicitly set
this bit to allow a legacy driver to work.
Indicates that the next item in the list is at offset 00h.
Indicates that this pointer is a message signaled interrupt
capability.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
HOT
5
Read/Write
8-bit
Core
5
Read-Only
16-bit
Core
to D0 transition.
Order Number: 300641-004US
Intel
®
6300ESB ICH—13
November 2007
Access
Access
R/W
RO
RO
RO