NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 538

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
538
Bits
Default Value:
4:2
®
Table 441. Offset 02h: HST_CNT—Host Control Register (Sheet 2 of 3)
6300ESB I/O Controller Hub
Device:
Offset:
SMB_CMD
31
02h
00h
Name
The bit encoding below indicates which command the Intel
6300ESB ICH is to perform. When enabled, the Intel
6300ESB ICH will generate an interrupt or SMI# when the
command has completed. When the value is for a non-
supported or reserved command, the Intel
set the device error (DEV_ERR) status bit and generate an
interrupt when the START bit is set. The Intel
will not operate until DEV_ERR is cleared.
000 = Quick: The slave address and read/write value (bit 0)
are stored in the transmit slave address register.
001 = Byte: This command uses the transmit slave address
and command registers. Bit 0 of the slave address register
determines if this is a read or write command.
010 = Byte Data: This command uses the transmit slave
address, command, and DATA0 registers. Bit 0 of the slave
address register determines if this is a read or write
command. When it is a read, the DATA0 register will contain
the read data.
011 = Word Data: This command uses the transmit slave
address, command, DATA0 and DATA1 registers. Bit 0 of the
slave address register determines if this is a read or write
command. When it is a read, after the command completes,
the DATA0 and DATA1 registers will contain the read data.
100 = Process Call: This command uses the transmit slave
address, command, DATA0 and DATA1 registers. Bit 0 of the
slave address register determines if this is a read or write
command. After the command completes, the DATA0 and
DATA1 registers will contain the read data.
101 = Block: This command uses the transmit slave
address, command, DATA0 registers, and the Block Data Byte
register. For block write, the count is stored in the DATA0
register and indicates how many bytes of data will be
transferred. For block reads, the count is received and stored
in the DATA0 register. Bit 0 of the slave address register
selects if this is a read or write command. For writes, data is
retrieved from the first n (where n is equal to the specified
count) addresses of the SRAM array. For reads, the data is
stored in the Block Data Byte register.
110 = I
address, command, DATA0, DATA1 registers, and the Block
Data Byte register. The read data is stored in the Block Data
Byte register. The Intel
data until the NAK is received.
111 = Block Process: This command uses the transmit
slave address, command, DATA0 and the Block Data Byte
register. For block write, the count is stored in the DATA0
register and indicates how many bytes of data will be
transferred. For block read, the count is received and stored
in the DATA0 register. Bit 0 of the slave address register
always indicate a write command. For writes, data is retrieved
from the first m (where m is equal to the specified count)
addresses of the SRAM array. For reads, the data is stored in
the Block Data Byte register.
NOTE: E32B bit in the Auxiliary Control register must be set
for this command to work.
2
C Read: This command uses the transmit slave
®
Description
6300ESB ICH will continue reading
Attribute:
Function:
Size:
3
Read/Write
8-bit
®
6300ESB ICH will
®
6300ESB ICH
Order Number: 300641-004US
®
Intel
®
®
6300ESB ICH—12
November 2007
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R/W