ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 105

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
Table 100. HcATLPTDSkipMap register: bit description
Table 101. HcATLLastPTD register: bit description
Table 102. HcATLCurrentActivePTD register: bit allocation
ISP1362_5
Product data sheet
Bit
31 to 0
Bit
31 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Symbol
SkipBits
[31:0]
Symbol
LastPTD
Bits[31:0]
14.9.6 HcATLLastPTD register (R/W: 1Dh/9Dh)
14.9.7 HcATLCurrentActivePTD register (R: 1Eh)
15
7
-
-
-
-
Access
R/W
This is a 32-bit register.
register represents the first PTD stored in the ATL buffer, bit 1 represents the second PTD
stored in the buffer, and so on. The bit that is set to logic 1 by the HCD is used as an
indication to the Host Controller that its corresponding PTD is the last PTD stored in the
ATL buffer. When the processing of the last PTD is complete, the Host Controller loops
back to process the first PTD stored in the buffer.
Code (Hex): 1D — read
Code (Hex): 9D — write
This register indicates which PTD stored in the ATL buffer is currently active and is
updated by the Host Controller. The HCD can use it as a buffer pointer to decide which
PTD locations are currently free to fill in new PTDs to the buffer. This indication helps to
prevent the HCD from accidentally writing into the currently active PTD buffer location.
Table 102
Code (Hex): 1E — read only
Table 103. HcATLCurrentActivePTD register: bit description
Bit
15 to 5
4 to 0
reserved
Access
R/W
14
6
-
-
-
-
Value
0000h
shows the bit allocation of the register.
Symbol
-
ActivePTD[4:0]
Value
0000h
13
5
-
-
-
-
Description
0 — The Host Controller processes the PTD.
1 — The Host Controller skips processing the PTD.
Table 101
Rev. 05 — 8 May 2007
Description
0 — The PTD is not the last PTD stored in the buffer.
1 — The PTD is the last PTD stored in the buffer.
Description
reserved
This 5-bit number represents the PTD that is currently active.
12
R
4
0
-
-
gives the bit description of the register. Bit 0 of the
reserved
11
R
3
0
-
-
ActivePTD[4:0]
Single-chip USB OTG Controller
10
R
2
0
-
-
R
9
1
0
-
-
© NXP B.V. 2007. All rights reserved.
ISP1362
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R
8
0
0
-
-