ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 111

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
Table 113. DcMode register: bit allocation
[1]
Table 115. DcHardwareConfiguration register: bit allocation
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
15.1.4 DcHardwareConfiguration register (R/W: BBh/BAh)
reserved
R/W
1
15
7
[1]
-
-
reserved
Code (Hex): B8/B9 — write or read DcMode register
Transaction — write or read 1 byte (code or data)
Table 114. DcMode register: bit description
This command is used to access the DcHardwareConfiguration register, which consists of
2 bytes. The first (lower) byte contains the device configuration and control values, the
second (upper) byte holds clock control bits and the clock division factor. The bit allocation
is given in
The DcHardwareConfiguration register controls the connection to the USB bus, clock
activity and power supply during the ‘suspend’ state, as well as output clock frequency,
DMA operating mode and pin configurations (polarity, signaling mode).
Code (Hex): BA/BB — write or read DcHardwareConfiguration register
Transaction — write or read 2 bytes (code or data)
Bit
7 to 6
5
4
3
2
1
0
EXTPUL
R/W
R/W
14
6
0
0
Symbol
-
GOSUSP
-
INTENA
DBGMOD
-
SOFTCT
Table
GOSUSP
115. A bus reset will not change any of programmed bit values.
NOLAZY
R/W
R/W
13
Description
reserved
Writing logic 1 followed by logic 0 will activate suspend mode.
reserved
Logic 1 enables all interrupts. Bus reset value: unchanged.
Logic 1 enables debug mode, in which all NAKs and errors will generate an
interrupt. Logic 0 selects normal operation, in which interrupts are generated
on every ACK (bulk or interrupt endpoints) or after every data transfer
(isochronous endpoints). Bus reset value: unchanged.
reserved
Logic 1 enables SoftConnect. This bit is ignored if EXTPUL = 1 in the
DcHardwareConfiguration register (see
unchanged.
Remark: In OTG mode, this bit is ignored. The LOC_CONN bit of the
OtgControl register controls the pull-up resistor on the OTG_DP1 pin.
5
0
1
Rev. 05 — 8 May 2007
CLKRUN
reserved
R/W
R/W
12
4
0
0
INTENA
R/W
R/W
0
11
3
0
[1]
DBGMOD
Single-chip USB OTG Controller
Table
R/W
R/W
0
10
2
0
[1]
CKDIV[3:0]
115). Bus reset value:
reserved
R/W
R/W
0
1
9
1
[1]
© NXP B.V. 2007. All rights reserved.
ISP1362
SOFTCT
110 of 152
R/W
R/W
0
0
8
1
[1]