ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 56

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
ISP1362_5
Product data sheet
12.4.1 Selecting an endpoint for the DMA transfer
12.4.2 8237 compatible mode
The target endpoint for DMA access is selected using bits EPDIX[3:0] of the
DcDMAConfiguration register, as shown in
is automatically set by the EPDIR bit in the associated ECR, to match the selected
endpoint type (OUT endpoint: read; IN endpoint: write).
Automatically asserting input DACK2 selects the endpoint specified in the
DcDMAConfiguration register, regardless of the current endpoint used for I/O mode
access.
Table 17.
This mode is selected by clearing the DAKOLY bit of the DcHardwareConfiguration
register (see
Table 18.
The DMA subsystem of an IBM-compatible PC is based on the Intel 8237 DMA controller.
It operates as a ‘fly-by’ DMA controller. Data is not stored in the DMA controller, but it is
transferred between an I/O port and a memory address. A typical example of the
Peripheral Controller in 8237 compatible DMA mode is given in
Endpoint
identifier
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Symbol Description
DREQ2 DMA request of Peripheral
DACK2
EOT
RD
WR
Controller
DMA acknowledge of Peripheral
Controller
end of transfer
read strobe
write strobe
Endpoint selection for the DMA transfer
8237 compatible mode: pin functions
Table
115). The pin functions for this mode are shown in
EPIDX[3:0]
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Rev. 05 — 8 May 2007
Transfer direction
EPDIR = 0
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
I/O
O
I
I
I
I
Table
17. The transfer direction (read or write)
Function
Peripheral Controller requests a DMA
transfer
DMA controller confirms the transfer
DMA controller terminates the transfer
instructs the Peripheral Controller to put
data on the bus
instructs the Peripheral Controller to get
data from the bus
Single-chip USB OTG Controller
Figure
EPDIR = 1
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
Table
26.
© NXP B.V. 2007. All rights reserved.
ISP1362
18.
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