ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 55

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
ISP1362_5
Product data sheet
12.3.5 Endpoint I/O mode access
12.3.6 Special actions on control endpoints
12.4 Peripheral Controller DMA transfer
When reset by hardware or by the USB bus occurs, the Peripheral Controller disables all
endpoints and clears all ECRs, except the control endpoint that is fixed and always
enabled.
An endpoint initialization can be done at any time. It is, however, valid only after
enumeration.
When an endpoint event occurs (a packet is transmitted or received), the associated
endpoint interrupt bits (EPn) of the DcInterrupt register (IR) are set by the SIE. The
firmware then responds to the interrupt and selects the endpoint for processing.
The endpoint interrupt bit is cleared by reading the DcEndpointStatus register (ESR). The
ESR also contains information on the status of the endpoint buffer.
For an OUT (= receive) endpoint, the packet length and packet data can be read from the
Peripheral Controller by using the Read Buffer command. When the whole packet has
been read, firmware sends a Clear Buffer command to enable the reception of new
packets.
For an IN (= transmit) endpoint, the packet length and data to be sent can be written to the
Peripheral Controller by using the Write Buffer command. When the whole packet has
been written to the buffer, firmware sends a Validate Buffer command to enable data
transmission to the host.
Control endpoints require special firmware actions. The arrival of a set-up packet flushes
the IN buffer and disables the Validate Buffer and Clear Buffer commands for the control
IN and OUT endpoints. The microprocessor must re-enable these commands by sending
an acknowledge set-up command to both the control endpoints.
This ensures that the last set-up packet stays in the buffer and that no packets can be sent
back to the host, until the microprocessor has explicitly acknowledged that it has received
the set-up packet.
Direct Memory Access (DMA) is a method to transfer data from one location to another in
a computer system, without the intervention of the CPU. Many different implementations
of DMA exist. The Peripheral Controller supports 8237 compatible mode.
8237 compatible mode: Based on the DMA subsystem of the IBM personal computers
(PC, AT and all its successors and clones). This architecture uses the Intel 8237 DMA
controller and has separate address spaces for memory and I/O.
The following features are supported:
•
•
•
•
Single-cycle or burst transfers (up to 16 bytes per cycle)
Programmable transfer direction (read or write)
Multiple End-Of-Transfer (EOT) sources: internal conditions, short or empty packet
Programmable signal levels on pins DREQ2 and DACK2
Rev. 05 — 8 May 2007
Single-chip USB OTG Controller
© NXP B.V. 2007. All rights reserved.
ISP1362
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