ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 31

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ISP1362EE

Manufacturer Part Number
ISP1362EE
Description
IC USB CTRL SNGL CHIP 64TFBGA
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1362EE

Controller Type
USB 2.0 Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-

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NXP Semiconductors
9. Power-On Reset (POR)
ISP1362_5
Product data sheet
When V
will typically be 800 ns. The pulse is started when V
To give a better view of the functionality,
dips at t2 to t3 and t4 to t5. If the dip at t4 to t5 is too short (that is, < 11 s), the internal
POR pulse will not react and will remain LOW. The internal POR starts with a HIGH at t0.
At t1, the detector will see the passing of the trip level and a delay element will add
another t
The internal POR pulse will be generated whenever V
11 s.
The RESET pin can be either connected to V
externally controlled (by the micro, ASIC, and so on).
the clock with respect to the external reset pulse.
Fig 15. Internal power-on reset timing
Fig 16. Clock with respect to the external power-on reset
t0
CC
(1) PORP = Power-On Reset Pulse.
Stable external clock is available at A.
PORP
is directly connected to the RESET pin, the internal POR pulse width (t
t1
before it drops to LOW.
t
PORP
EXTERNAL CLOCK
Rev. 05 — 8 May 2007
RESET
t2
Figure 15
CC
t3
t
(using the internal POR circuit) or
PORP
A
shows a possible curve of V
CC
Figure 16
CC
rises above V
Single-chip USB OTG Controller
drops below V
004aaa484
t4
shows the availability of
t5
trip
© NXP B.V. 2007. All rights reserved.
trip
(2.03 V).
ISP1362
for more than
004aaa482
PORP
V
V
CC
CC
trip
with
30 of 152
PORP
(1)
)

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